ep0_state
enum dwc2_ep0_state ep0_state;
dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
switch (hsotg->ep0_state) {
hsotg->ep0_state);
hs->ep0_state == DWC2_EP0_DATA_OUT)
hsotg->ep0_state = DWC2_EP0_STATUS_IN;
hsotg->ep0_state = DWC2_EP0_DATA_IN;
hsotg->ep0_state = DWC2_EP0_DATA_OUT;
hsotg->ep0_state = DWC2_EP0_SETUP;
hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
if (hsotg->ep0_state == DWC2_EP0_SETUP)
WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
hsotg->ep0_state == DWC2_EP0_SETUP && !(ints & DXEPINT_SETUP))
if (hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
enum ep0_state state; /* P: lock */
enum ep0_state state;
enum ep0_state state;
enum bdc_ep0_state ep0_state;
bdc->ep0_state = WAIT_FOR_SETUP;
__func__, ep0_state_string[bdc->ep0_state]);
bdc->ep0_state = WAIT_FOR_STATUS_START;
bdc->ep0_state = WAIT_FOR_DATA_START;
__func__, ep0_state_string[bdc->ep0_state]);
bdc->ep0_state = WAIT_FOR_DATA_START;
bdc->ep0_state = WAIT_FOR_DATA_XMIT;
if (bdc->ep0_state != WAIT_FOR_DATA_START)
ep0_state_string[bdc->ep0_state]);
bdc->ep0_state = WAIT_FOR_DATA_XMIT;
"ep0_state:%s", ep0_state_string[bdc->ep0_state]);
__func__, ep0_state_string[bdc->ep0_state]);
if ((bdc->ep0_state != WAIT_FOR_STATUS_START) &&
(bdc->ep0_state != WAIT_FOR_DATA_XMIT))
ep0_state_string[bdc->ep0_state]);
if (bdc->ep0_state == WAIT_FOR_DATA_XMIT) {
bdc->ep0_state = STATUS_PENDING;
bdc->ep0_state = WAIT_FOR_STATUS_XMIT;
"ep0_state:%s", ep0_state_string[bdc->ep0_state]);
switch (bdc->ep0_state) {
bdc->ep0_state = WAIT_FOR_STATUS_START;
bdc->ep0_state = WAIT_FOR_SETUP;
ep0_state_string[bdc->ep0_state]);
switch (bdc->ep0_state) {
ep0_state_string[bdc->ep0_state]);
if (bdc->ep0_state == WAIT_FOR_STATUS_START) {
bdc->ep0_state = WAIT_FOR_STATUS_XMIT;
bdc->ep0_state = WAIT_FOR_SETUP;
if ((ep->epnum == 0) && (udc->ep0_state == DATA_STATE_NEED_ZLP))
udc->ep0_state = DATA_STATE_NEED_ZLP;
udc->ep0_state = WAIT_FOR_OUT_STATUS;
switch (udc->ep0_state) {
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
ep->udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = DATA_STATE_XMIT;
udc->ep0_state = DATA_STATE_RECV;
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = DATA_STATE_XMIT;
udc->ep0_state = DATA_STATE_RECV;
udc->ep0_state = DATA_STATE_NEED_ZLP;
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
&& (udc->ep0_state == WAIT_FOR_SETUP)) {
udc->ep0_state = WAIT_FOR_SETUP;
u32 ep0_state; /* Endpoint zero state */
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
if (udc->ep0_state != DATA_STATE_XMIT)
udc->ep0_state = WAIT_FOR_OUT_STATUS;
udc->ep0_state = DATA_STATE_XMIT;
udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
if (udc->ep0_state == DATA_STATE_XMIT)
udc->ep0_state = WAIT_FOR_OUT_STATUS;
switch (udc->ep0_state) {
udc->ep0_state = WAIT_FOR_OUT_STATUS;
udc->ep0_state = WAIT_FOR_SETUP;
udc->ep0_state = WAIT_FOR_SETUP;
udc_controller->ep0_state = WAIT_FOR_SETUP;
udc_controller->ep0_state = WAIT_FOR_SETUP;
udc_controller->ep0_state = WAIT_FOR_SETUP;
u32 ep0_state; /* Endpoint zero state */
enum ep0_state ep0state;
enum ep0_state ep0state;
if (WARN_ON(udc->ep0_state == ISP1760_CTRL_SETUP || !stall ||
udc->ep0_state = ISP1760_CTRL_SETUP;
udc->ep0_state = ISP1760_CTRL_SETUP;
udc->ep0_state = ISP1760_CTRL_SETUP;
udc->ep0_state = ISP1760_CTRL_SETUP;
if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_OUT) {
udc->ep0_state);
if (ep->addr == 0 && udc->ep0_state != ISP1760_CTRL_DATA_IN) {
udc->ep0_state);
if (udc->ep0_state != ISP1760_CTRL_SETUP) {
udc->ep0_state = ISP1760_CTRL_STATUS;
udc->ep0_state = ISP1760_CTRL_DATA_IN;
udc->ep0_state = ISP1760_CTRL_DATA_OUT;
udc->ep0_state != ISP1760_CTRL_DATA_IN) {
switch (udc->ep0_state) {
enum isp1760_ctrl_state ep0_state;
enum mtu3_g_ep0_state ep0_state;
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
switch (mtu->ep0_state) {
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
mtu->ep0_state = MU3D_EP0_STATE_TX_END;
mtu->ep0_state = MU3D_EP0_STATE_TX;
mtu->ep0_state = MU3D_EP0_STATE_RX;
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
switch (mtu->ep0_state) {
mtu->ep0_state = MU3D_EP0_STATE_SETUP;
switch (mtu->ep0_state) {
if (mtu->ep0_state == MU3D_EP0_STATE_TX)
switch (mtu->ep0_state) {
enum musb_g_ep0_state ep0_state;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
switch (musb->ep0_state) {
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
musb_dbg(musb, "ep0 can't halt in state %d", musb->ep0_state);
musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
musb->ep0_state = MUSB_EP0_STAGE_TX;
musb->ep0_state = MUSB_EP0_STAGE_RX;
csr, len, decode_ep0stage(musb->ep0_state));
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
switch (musb->ep0_state) {
musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
decode_ep0stage(musb->ep0_state));
switch (musb->ep0_state) {
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
musb->ep0_state = MUSB_EP0_STAGE_SETUP;
switch (musb->ep0_state) {
musb->ep0_state =
musb->ep0_state =
decode_ep0stage(musb->ep0_state));
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
switch (musb->ep0_state) {
musb->ep0_state);
if (musb->ep0_state == MUSB_EP0_STAGE_TX)
else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;