ene_write_reg
ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
ene_write_reg(dev, ENE_CIRCFG2, 0x00);
ene_write_reg(dev, ENE_CIRRLC_CFG,
ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
ene_write_reg(dev, ENE_IRQ, reg_value);
ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
ene_write_reg(dev, ENE_CIRCFG, conf1);
ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
ene_write_reg(dev,
ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);