drivers/gpu/drm/amd/pm/powerplay/hwmgr/pppcielanes.h

27

extern uint8_t encode_pcie_lane_width(uint32_t num_lanes);

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1280

pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c

1283

pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c

1009

(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/fiji_smumgr.c

839

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/smumgr/iceland_smumgr.c

776

(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

828

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(

drivers/gpu/drm/amd/pm/powerplay/smumgr/tonga_smumgr.c

519

(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);

drivers/gpu/drm/amd/pm/powerplay/smumgr/vegam_smumgr.c

582

table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(