drivers/gpu/drm/amd/amdgpu/si.c

1794

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1811

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1814

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1817

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1821

r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

1826

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1835

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1853

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1858

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/amd/amdgpu/si.c

1860

r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/evergreen.c

1201

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/evergreen.c

1205

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/evergreen.c

1216

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

drivers/gpu/drm/radeon/evergreen.c

1219

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/evergreen.c

1220

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/evergreen.c

1223

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/evergreen.c

1227

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/evergreen.c

1232

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/evergreen.c

1241

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/evergreen.c

1257

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/evergreen.c

1262

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/evergreen.c

1264

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/r600.c

214

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~(

drivers/gpu/drm/radeon/r600.c

223

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/r600.c

243

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/r600.c

248

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/r600.c

252

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK,

drivers/gpu/drm/radeon/r600.c

256

WREG32_P(CG_UPLL_FUNC_CNTL,

drivers/gpu/drm/radeon/r600.c

272

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/r600.c

277

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/r600.c

282

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv770.c

102

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/rv770.c

117

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/rv770.c

122

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/rv770.c

125

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv770.c

70

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/rv770.c

88

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));

drivers/gpu/drm/radeon/rv770.c

91

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/rv770.c

94

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/rv770.c

99

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

6986

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/si.c

7003

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);

drivers/gpu/drm/radeon/si.c

7006

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);

drivers/gpu/drm/radeon/si.c

7009

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7013

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);

drivers/gpu/drm/radeon/si.c

7018

WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7027

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);

drivers/gpu/drm/radeon/si.c

7043

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);

drivers/gpu/drm/radeon/si.c

7048

WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);

drivers/gpu/drm/radeon/si.c

7050

r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);