emit_wait
cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_EQ_SDD, 1);
cs = emit_wait(cs, offset + 4008, MI_SEMAPHORE_SAD_NEQ_SDD, 1);
bool emit_wait)
unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
if (emit_wait && ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
bool emit_wait)
u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
bool emit_wait)
bool emit_wait)
unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
if (emit_wait && (rdev->family >= CHIP_CEDAR)) {
bool emit_wait)
u32 s = emit_wait ? 0 : 1;
bool emit_wait);
struct radeon_semaphore *semaphore, bool emit_wait);
#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)]->emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
bool emit_wait);
bool emit_wait);
bool emit_wait);
bool emit_wait);
bool emit_wait);
bool emit_wait);
bool emit_wait);
bool emit_wait);
bool emit_wait)
radeon_ring_write(ring, cpu_to_le32(0x01003000 | (emit_wait ? 1 : 0)));
if (!emit_wait)
bool emit_wait)
bool emit_wait)
radeon_ring_write(ring, emit_wait ? 1 : 0);
bool emit_wait)
radeon_ring_write(ring, 0x80 | (emit_wait ? 1 : 0));