em28xx_write_regs
em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x07", 1);
em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
em28xx_write_regs(dev, 0x0d, "\x42", 1);
em28xx_write_regs(dev, 0x08, "\xfd", 1);
em28xx_write_regs(dev, 0x08, "\xff", 1);
em28xx_write_regs(dev, 0x08, "\x7f", 1);
em28xx_write_regs(dev, 0x08, "\x6b", 1);
em28xx_write_regs(dev, 0x08, "\xf8", 1);
dev->em28xx_write_regs = em28xx_write_regs;
EXPORT_SYMBOL_GPL(em28xx_write_regs);
return em28xx_write_regs(dev, reg, &val, 1);
return em28xx_write_regs(dev, reg, &newval, 1);
ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
ret = em28xx_write_regs(dev, EM28XX_R40_AC97LSB, (u8 *)&value, 2);
ret = em28xx_write_regs(dev, EM28XX_R42_AC97ADDR, &addr, 1);
ret = em28xx_write_regs(dev, EM2800_R08_AUDIOSRC, &input, 1);
ret = dev->em28xx_write_regs(dev, 0x04, buf2, 2);
ret = dev->em28xx_write_regs(dev, 4 - len, &b2[4 - len], 2 + len);
if (WARN_ON(!dev->em28xx_write_regs || !dev->em28xx_read_reg ||
em28xx_write_regs(dev, EM2874_R50_IR_CONFIG, &ir_config, 1);
return em28xx_write_regs(dev, reg->reg, (char *)&buf,
em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
int (*em28xx_write_regs)(struct em28xx *dev, u16 reg,
int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len);