drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3129

struct dwbc *dwb = params->dwbc_enable_params.dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3138

struct dwbc *dwb = params->dwbc_disable_params.dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3146

struct dwbc *dwb = params->dwbc_update_params.dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4103

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4187

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4199

struct dwbc *dwb)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

598

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

619

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

640

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

652

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

670

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

750

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

45

static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

47

(void)dwbc;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

65

static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

68

struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

71

dwbc->funcs->disable(dwbc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

83

static bool dwb1_disable(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

85

struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

254

struct dwbc base;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

101

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

121

dwb2_config_dwb_cnv(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

124

dwb2_set_scaler(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

135

bool dwb2_disable(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

137

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

158

static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

160

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

185

dwb2_config_dwb_cnv(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

188

dwb2_set_scaler(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

198

bool dwb2_is_enabled(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

200

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

210

void dwb2_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

213

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

226

void dwb2_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

229

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

235

static void dwb2_set_warmup(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

238

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

250

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

252

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

50

static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

52

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

72

void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

74

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

99

static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

389

struct dwbc base;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

402

bool dwb2_disable(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

404

bool dwb2_is_enabled(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

406

void dwb2_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

409

void dwb2_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

412

void dwb2_config_dwb_cnv(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

415

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

101

dwb3_config_fc(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

104

dwb3_program_hdr_mult(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

105

dwb3_set_gamut_remap(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

106

dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

109

dwb3_set_denorm(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

120

bool dwb3_disable(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

122

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

130

DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

134

void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

136

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

152

DC_LOG_DWB("%s dwb3_fc_disabled at inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

156

bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

158

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

168

DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

176

dwb3_config_fc(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

179

dwb3_program_hdr_mult(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

180

dwb3_set_gamut_remap(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

181

dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

184

dwb3_set_denorm(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

194

bool dwb3_is_enabled(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

196

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

206

void dwb3_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

209

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

221

void dwb3_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

224

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

229

void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

231

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

46

static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

48

(void)dwbc;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

67

void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

69

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

89

dwb3_set_stereo(dwbc, &params->stereo_params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

92

bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

94

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

95

DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

871

struct dwbc base;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

884

bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

886

bool dwb3_disable(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

888

bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

890

bool dwb3_is_enabled(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

892

void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

894

void dwb3_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

897

void dwb3_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

900

void dwb3_config_fc(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

903

void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

906

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

910

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

914

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

273

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

276

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

286

cm_helper_translate_curve_to_hw_format(dwbc->ctx,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

301

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

306

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

356

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

359

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

365

dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

379

dwb3_program_gamut_remap(dwbc, arr_reg_val,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

382

dwb3_program_gamut_remap(dwbc, arr_reg_val,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

389

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

392

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2544

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2550

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2570

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2574

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3242

res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

334

res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

459

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

460

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

476

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

482

dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

533

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

536

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

559

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

563

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

582

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

629

dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3311

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3347

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3370

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3376

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3403

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3409

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3429

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3435

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

118

dc->res_pool->dwbc[i]->mcif = dc->res_pool->mcif_wb[i];

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2094

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2122

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2126

struct dwbc *dwb);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

534

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

539

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

543

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

266

struct dwbc *dwbc[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

506

struct dwbc *dwbc;

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

177

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

181

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

184

bool (*disable)(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

187

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

191

struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

194

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

198

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

202

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

206

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

211

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

215

struct dwbc *dwbc, unsigned int *buf_idx,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

220

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

225

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

230

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

234

struct dwbc *dwbc, uint32_t *time_stamp);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

237

struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1185

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1186

kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1187

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2310

pool->dwbc[i] = &dwbc20->base;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

748

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

749

kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

750

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1299

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1300

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1301

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1393

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1148

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1149

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1150

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1231

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1206

if (pool->dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1207

kfree(TO_DCN30_DWBC(pool->dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1208

pool->dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

842

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1150

if (pool->dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1151

kfree(TO_DCN30_DWBC(pool->dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1152

pool->dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

803

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1599

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1600

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1601

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1690

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1658

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1659

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1660

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1749

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1601

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1602

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1603

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1692

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1594

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1595

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1596

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1682

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1611

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1612

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1613

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1696

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1585

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1586

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1587

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1670

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1660

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1661

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1662

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1776

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1640

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1641

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1642

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1756

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1647

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1648

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1649

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1763

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1601

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1602

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1603

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1687

pool->dwbc[i] = &dwbc401->base;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1593

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1594

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1595

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1742

pool->dwbc[i] = &dwbc42->base;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1560

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1561

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1562

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1707

pool->dwbc[i] = &dwbc42->base;