arch/mips/lantiq/xway/clk.c

177

unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;

arch/mips/lantiq/xway/clk.c

22

#define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]

arch/mips/lantiq/xway/clk.c

249

unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;

arch/mips/lantiq/xway/clk.c

333

unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 0x7;

arch/mips/lantiq/xway/clk.c

35

if (ltq_cgu_r32(CGU_SYS) & 0x40)

arch/mips/lantiq/xway/clk.c

42

switch (ltq_cgu_r32(CGU_SYS) & 0xc) {

arch/mips/lantiq/xway/clk.c

56

unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;

arch/mips/lantiq/xway/clk.c

79

if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)

arch/mips/lantiq/xway/clk.c

88

if (ltq_cgu_r32(CGU_SYS) & BIT(0))

arch/mips/lantiq/xway/clk.c

96

if (ltq_cgu_r32(CGU_SYS) & BIT(2))

arch/mips/lantiq/xway/sysctrl.c

526

if (ltq_cgu_r32(CGU_SYS) & (1 << 5))