CGU_CLK_MUX
if (clk_info->type & CGU_CLK_MUX) {
if (clk_info->type & CGU_CLK_MUX) {
if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) {
if (caps & CGU_CLK_MUX)
if (caps & CGU_CLK_MUX) {
caps &= ~(CGU_CLK_MUX | CGU_CLK_MUX_GLITCHFREE);
"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"udc", CGU_CLK_MUX | CGU_CLK_DIV,
"rtc", CGU_CLK_MUX,
"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
"tve", CGU_CLK_MUX | CGU_CLK_GATE,
"rtc", CGU_CLK_MUX | CGU_CLK_GATE,
"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
"tve", CGU_CLK_GATE | CGU_CLK_MUX,
"lpclk", CGU_CLK_GATE | CGU_CLK_MUX,
"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"i2s", CGU_CLK_DIV | CGU_CLK_MUX,
"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
"rtc", CGU_CLK_MUX,
"mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
"pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX,
"i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"rtc", CGU_CLK_MUX,
"sclk_a", CGU_CLK_MUX,
"cpumux", CGU_CLK_MUX,
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
"ahb2_apb_mux", CGU_CLK_MUX,
"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
"vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"i2s", CGU_CLK_MUX,
"lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
"lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
"msc_mux", CGU_CLK_MUX,
"uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"ssi", CGU_CLK_MUX,
"cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
"pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"pcm", CGU_CLK_MUX | CGU_CLK_GATE,
"gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
"sclk_a", CGU_CLK_MUX,
"cpu_mux", CGU_CLK_MUX,
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
"ahb2_apb_mux", CGU_CLK_MUX,
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"i2s_pll_mux", CGU_CLK_MUX,
"i2s", CGU_CLK_MUX,
"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"msc_mux", CGU_CLK_MUX,
"otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"ssi_mux", CGU_CLK_MUX,
"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
"sclk_a", CGU_CLK_MUX,
"cpu_mux", CGU_CLK_MUX,
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
"ahb2_apb_mux", CGU_CLK_MUX,
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"msc_mux", CGU_CLK_MUX,
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"ssi_mux", CGU_CLK_MUX,
"rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,