CGU_CLK_DIV
if (clk_info->type & CGU_CLK_DIV) {
if (clk_info->type & CGU_CLK_DIV)
if (clk_info->type & CGU_CLK_DIV) {
if (caps & CGU_CLK_DIV) {
caps &= ~CGU_CLK_DIV;
"hclk", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV,
"mclk", CGU_CLK_DIV,
"ipu", CGU_CLK_DIV | CGU_CLK_GATE,
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"mmc_mux", CGU_CLK_DIV,
"udc", CGU_CLK_MUX | CGU_CLK_DIV,
"pll half", CGU_CLK_DIV,
"cclk", CGU_CLK_DIV,
"cclk", CGU_CLK_DIV,
"hclk", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV,
"mclk", CGU_CLK_DIV,
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
"lcd_pclk", CGU_CLK_DIV,
"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"pll half", CGU_CLK_DIV,
"hclk", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV,
"mclk", CGU_CLK_DIV,
"h1clk", CGU_CLK_DIV,
"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
"mmc", CGU_CLK_DIV,
"i2s", CGU_CLK_MUX | CGU_CLK_DIV,
"spi", CGU_CLK_DIV | CGU_CLK_GATE,
"cim", CGU_CLK_DIV | CGU_CLK_GATE,
"pll half", CGU_CLK_DIV,
"ext half", CGU_CLK_DIV,
"cclk", CGU_CLK_DIV,
"cclk", CGU_CLK_DIV,
"hclk", CGU_CLK_DIV,
"sclk", CGU_CLK_DIV,
"h2clk", CGU_CLK_DIV,
"mclk", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV,
"pll0_half", CGU_CLK_DIV,
"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"lpclk_div", CGU_CLK_DIV | CGU_CLK_MUX,
"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"pcm", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"i2s", CGU_CLK_DIV | CGU_CLK_MUX,
"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"mmc_mux", CGU_CLK_MUX | CGU_CLK_DIV,
"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
"cim", CGU_CLK_DIV | CGU_CLK_GATE,
"cclk", CGU_CLK_DIV,
"h0clk", CGU_CLK_DIV,
"h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
"h2clk", CGU_CLK_DIV,
"c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
"pclk", CGU_CLK_DIV,
"mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"uhc", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"gpu", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"bch", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"lpclk", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"gps", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"ssi_mux", CGU_CLK_DIV | CGU_CLK_MUX,
"pcm_mux", CGU_CLK_DIV | CGU_CLK_MUX,
"i2s", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"usb", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"cpu", CGU_CLK_DIV,
"l2cache", CGU_CLK_DIV,
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
"ahb2", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV,
"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
"vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
"lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
"msc2", CGU_CLK_DIV | CGU_CLK_GATE,
"uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
"pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
"l2cache", CGU_CLK_DIV,
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
"ahb2", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV | CGU_CLK_GATE,
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
"otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
"cpu", CGU_CLK_DIV | CGU_CLK_GATE,
"l2cache", CGU_CLK_DIV,
"ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
"ahb2", CGU_CLK_DIV,
"pclk", CGU_CLK_DIV | CGU_CLK_GATE,
"ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,