dsi_write_reg
dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
dsi_write_reg(dsi, DSI_TIMING1, l);
dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
dsi_write_reg(dsi, DSI_TIMING1, r);
dsi_write_reg(dsi, DSI_VC_CTRL(vc), r);
dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(vc), val);
dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(vc), val);
dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc), r);
dsi_write_reg(dsi, DSI_TIMING2, r);
dsi_write_reg(dsi, DSI_TIMING1, r);
dsi_write_reg(dsi, DSI_TIMING1, r);
dsi_write_reg(dsi, DSI_TIMING2, r);
dsi_write_reg(dsi, DSI_CTRL, r);
dsi_write_reg(dsi, DSI_CTRL, r);
dsi_write_reg(dsi, DSI_VM_TIMING4, r);
dsi_write_reg(dsi, DSI_VM_TIMING5, r);
dsi_write_reg(dsi, DSI_VM_TIMING6, r);
dsi_write_reg(dsi, DSI_CTRL, r);
dsi_write_reg(dsi, DSI_CLK_TIMING, r);
dsi_write_reg(dsi, DSI_VM_TIMING7, r);
dsi_write_reg(dsi, DSI_VM_TIMING1, r);
dsi_write_reg(dsi, DSI_VM_TIMING2, r);
dsi_write_reg(dsi, DSI_VM_TIMING3, r);
dsi_write_reg(dsi, DSI_VC_TE(vc), l);
dsi_write_reg(dsi, DSI_VC_TE(vc), l);
dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
dsi_write_reg(dsi, enable_reg, mask);
dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
dsi_write_reg(dsidev, DSI_TIMING1, l);
dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
dsi_write_reg(dsidev, DSI_TIMING1, r);
dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
dsi_write_reg(dsidev, DSI_TIMING2, r);
dsi_write_reg(dsidev, DSI_TIMING1, r);
dsi_write_reg(dsidev, DSI_TIMING1, r);
dsi_write_reg(dsidev, DSI_TIMING2, r);
dsi_write_reg(dsidev, DSI_CTRL, r);
dsi_write_reg(dsidev, DSI_CTRL, r);
dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
dsi_write_reg(dsidev, DSI_CTRL, r);
dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
dsi_write_reg(dsidev, enable_reg, mask);