drivers/gpu/drm/bridge/tc358768.c

1009

dsiclk_ps = (u32)div_u64(PICO, dsiclk);

drivers/gpu/drm/bridge/tc358768.c

166

u32 dsiclk; /* pll_clk / 2 */

drivers/gpu/drm/bridge/tc358768.c

435

priv->dsiclk = best_pll / 2;

drivers/gpu/drm/bridge/tc358768.c

724

priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);

drivers/gpu/drm/bridge/tc358768.c

726

tc358768_pll_to_pclk(priv, priv->dsiclk * 2),

drivers/gpu/drm/bridge/tc358768.c

764

u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes;

drivers/gpu/drm/bridge/tc358768.c

773

u64 n = priv->dsiclk / 4 * priv->dsi_lanes;

drivers/gpu/drm/bridge/tc358768.c

790

u32 dsiclk, hsbyteclk;

drivers/gpu/drm/bridge/tc358768.c

829

dsiclk = priv->dsiclk;

drivers/gpu/drm/bridge/tc358768.c

830

hsbyteclk = dsiclk / 4;

drivers/gpu/drm/bridge/tc358775.c

380

u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;

drivers/gpu/drm/bridge/tc358775.c

439

dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;

drivers/gpu/drm/bridge/tc358775.c

440

clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);

drivers/gpu/drm/bridge/tc358775.c

441

byteclk = dsiclk / 4;

drivers/mfd/db8500-prcmu.c

1348

val &= ~dsiclk[n].divsel_mask;

drivers/mfd/db8500-prcmu.c

1349

val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<

drivers/mfd/db8500-prcmu.c

1350

dsiclk[n].divsel_shift);

drivers/mfd/db8500-prcmu.c

1507

divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);

drivers/mfd/db8500-prcmu.c

1510

divsel = dsiclk[n].divsel;

drivers/mfd/db8500-prcmu.c

1512

dsiclk[n].divsel = divsel;

drivers/mfd/db8500-prcmu.c

1881

dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :

drivers/mfd/db8500-prcmu.c

1886

val &= ~dsiclk[n].divsel_mask;

drivers/mfd/db8500-prcmu.c

1887

val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);

drivers/mfd/db8500-prcmu.c

507

static struct dsiclk dsiclk[2] = {