eeprom_buf
const u8 *p = eeprom_buf;
buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
msgs[1].buf = eeprom_buf;
return r < 0 ? r : eeprom_buf - p;
u8 *eeprom_buf, u32 buf_size, bool read)
eeprom_buf, buf_size, read);
buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {
eeprom_buf, ps, read);
u32 eeprom_addr, u8 *eeprom_buf,
return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
u32 eeprom_addr, u8 *eeprom_buf,
return amdgpu_eeprom_xfer(i2c_adap, eeprom_addr, eeprom_buf, bytes,
u8 *eeprom_buf, u32 buf_size, bool read)
u32 eeprom_addr, u8 *eeprom_buf,
u32 eeprom_addr, u8 *eeprom_buf,
const u8 *p = eeprom_buf;
buf_size -= len, eeprom_addr += len, eeprom_buf += len) {
msgs[1].buf = eeprom_buf;
return r < 0 ? r : eeprom_buf - p;
u8 *eeprom_buf, u32 buf_size, bool read)
u32 eeprom_addr, u8 *eeprom_buf, u32 buf_size, bool read);
u8 *eeprom_buf, u32 buf_size, bool read)
eeprom_addr, eeprom_buf, buf_size, read);
u8 *eeprom_buf, u32 buf_size, bool read)
eeprom_buf, buf_size, read);
buf_size -= ps, eeprom_addr += ps, eeprom_buf += ps) {
eeprom_buf, ps, read);
u32 eeprom_addr, u8 *eeprom_buf, u32 bytes)
eeprom_buf, bytes, true);
u32 eeprom_addr, u8 *eeprom_buf, u32 bytes)
eeprom_buf, bytes, false);
BUILD_BUG_ON(offsetof(struct eeprom_buf, data) % 8);
offsetof(struct eeprom_buf, data) / NSP_SFF_EEPROM_BLOCK_LEN;
static char eeprom_buf[HPEE_MAX_LENGTH];
eeprom_buf[i] = gsc_readb(eeprom_addr+i);
eh = (struct eeprom_header*)(eeprom_buf);
(&eeprom_buf[HPEE_SLOT_INFO(i)]);
if (parse_slot_config(i+1, &eeprom_buf[es->config_data_offset],