drivers/gpu/drm/amd/display/dc/core/dc.c

7466

struct dscl_prog_data *dscl_data = &pipe_ctx->plane_res.scl_data.dscl_prog_data;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1572

spl_out->dscl_prog_data = resource_get_dscl_prog_data(pipe_ctx);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5936

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5938

return &pipe_ctx->plane_res.scl_data.dscl_prog_data;

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

223

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

225

populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

227

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

229

populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->viewport_c);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

231

populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps);

drivers/gpu/drm/amd/display/dc/dc_spl_translate.c

233

populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1000

ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1002

ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1003

ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1004

ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1006

ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1007

ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1008

ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1010

ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1011

ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1012

ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1014

ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1015

ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1016

ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1018

ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1019

ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1023

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1027

ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1028

ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1029

ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1030

ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1031

ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1032

ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1035

if (scl_data->dscl_prog_data.filter_blur_scale_v) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1039

scl_data->dscl_prog_data.filter_blur_scale_v);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1042

if (scl_data->dscl_prog_data.filter_blur_scale_h) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1046

scl_data->dscl_prog_data.filter_blur_scale_h);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1096

if (scl_data->dscl_prog_data.isharp_en &&

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1097

(dpp->scl_data.dscl_prog_data.sharpness_level

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1098

!= scl_data->dscl_prog_data.sharpness_level)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1100

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1101

dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1102

memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1113

dscl_mode = (enum dcn401_dscl_mode_sel) scl_data->dscl_prog_data.dscl_mode;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1114

rect = (struct rect *)&scl_data->dscl_prog_data.recout;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1115

mpc_width = scl_data->dscl_prog_data.mpc_size.width;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1116

mpc_height = scl_data->dscl_prog_data.mpc_size.height;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1117

v_num_taps = scl_data->dscl_prog_data.taps.v_taps;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1118

v_num_taps_c = scl_data->dscl_prog_data.taps.v_taps_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1119

h_num_taps = scl_data->dscl_prog_data.taps.h_taps;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1120

h_num_taps_c = scl_data->dscl_prog_data.taps.h_taps_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

295

filter_h = scl_data->dscl_prog_data.filter_h;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

296

filter_v = scl_data->dscl_prog_data.filter_v;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

298

filter_h_c = scl_data->dscl_prog_data.filter_h_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

299

filter_v_c = scl_data->dscl_prog_data.filter_v_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

529

SCL_H_SCALE_RATIO, data->dscl_prog_data.ratios.h_scale_ratio);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

532

SCL_V_SCALE_RATIO, data->dscl_prog_data.ratios.v_scale_ratio);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

535

SCL_H_SCALE_RATIO_C, data->dscl_prog_data.ratios.h_scale_ratio_c);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

538

SCL_V_SCALE_RATIO_C, data->dscl_prog_data.ratios.v_scale_ratio_c);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

541

SCL_H_INIT_FRAC, data->dscl_prog_data.init.h_filter_init_frac,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

542

SCL_H_INIT_INT, data->dscl_prog_data.init.h_filter_init_int);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

545

SCL_H_INIT_FRAC_C, data->dscl_prog_data.init.h_filter_init_frac_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

546

SCL_H_INIT_INT_C, data->dscl_prog_data.init.h_filter_init_int_c);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

549

SCL_V_INIT_FRAC, data->dscl_prog_data.init.v_filter_init_frac,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

550

SCL_V_INIT_INT, data->dscl_prog_data.init.v_filter_init_int);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

554

SCL_V_INIT_FRAC_BOT, data->dscl_prog_data.init.v_filter_init_bot_frac,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

555

SCL_V_INIT_INT_BOT, data->dscl_prog_data.init.v_filter_init_bot_int);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

559

SCL_V_INIT_FRAC_C, data->dscl_prog_data.init.v_filter_init_frac_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

560

SCL_V_INIT_INT_C, data->dscl_prog_data.init.v_filter_init_int_c);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

564

SCL_V_INIT_FRAC_BOT_C, data->dscl_prog_data.init.v_filter_init_bot_frac_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

565

SCL_V_INIT_INT_BOT_C, data->dscl_prog_data.init.v_filter_init_bot_int_c);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

671

SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

672

SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

673

SCL_EASF_V_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_v_ring);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

675

if (!scl_data->dscl_prog_data.easf_v_en) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

682

SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

683

SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

684

SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

685

SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

686

SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

687

SCL_EASF_V_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_v_bf2_roc_gain);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

690

SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

691

SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt_max);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

693

SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

694

SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

696

SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

697

SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

700

SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

701

SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

704

SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

705

SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

708

SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

709

SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

710

SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

711

SCL_EASF_V_BF_MINB, scl_data->dscl_prog_data.easf_v_bf_minb);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

714

SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

715

SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

716

SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

718

SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

719

SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

720

SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

722

SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

723

SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

724

SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

726

SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

727

SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

728

SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

730

SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

731

SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

732

SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg4);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

734

SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

735

SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

736

SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg5);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

738

SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

739

SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

740

SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg6);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

742

SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

743

SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg7);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

746

SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

747

SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

748

SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

750

SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

751

SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

752

SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

754

SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

755

SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

756

SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

758

SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

759

SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

760

SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

762

SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

763

SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

764

SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set4);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

766

SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

767

SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set5);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

786

SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

787

SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

788

SCL_EASF_H_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_h_ring);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

790

if (!scl_data->dscl_prog_data.easf_h_en) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

797

SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

798

SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

799

SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

800

SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

801

SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

802

SCL_EASF_H_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_h_bf2_roc_gain);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

805

SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

806

SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

809

SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

810

SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

813

SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

814

SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

815

SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

816

SCL_EASF_H_BF_MINB, scl_data->dscl_prog_data.easf_h_bf_minb);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

819

SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

820

SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

821

SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

823

SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

824

SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

825

SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

827

SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

828

SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

829

SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

831

SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

832

SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

833

SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

835

SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

836

SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

837

SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg4);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

839

SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

840

SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

841

SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg5);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

843

SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

844

SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

845

SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg6);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

847

SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

848

SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg7);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

851

SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

852

SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

853

SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set0);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

855

SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

856

SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

857

SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

859

SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

860

SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

861

SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set2);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

863

SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

864

SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

865

SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

867

SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

868

SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

869

SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set4);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

871

SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

872

SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set5);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

891

SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

892

SCL_SC_LTONL_EN, scl_data->dscl_prog_data.easf_ltonl_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

895

SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

896

SCL_SC_MATRIX_C1, scl_data->dscl_prog_data.easf_matrix_c1);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

898

SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

899

SCL_SC_MATRIX_C3, scl_data->dscl_prog_data.easf_matrix_c3);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

920

SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

923

SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

976

ISHARP_EN, scl_data->dscl_prog_data.isharp_en,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

977

ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

978

ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

979

ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

980

ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

981

ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

984

if (scl_data->dscl_prog_data.isharp_en) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

987

ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

988

ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

992

ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

993

ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

994

ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

998

ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0],

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

999

ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0],

drivers/gpu/drm/amd/display/dc/inc/hw/transform.h

166

struct dscl_prog_data dscl_prog_data;

drivers/gpu/drm/amd/display/dc/inc/resource.h

655

struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1195

static void spl_set_manual_ratio_init_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1200

dscl_prog_data->ratios.h_scale_ratio = SPL_NAMESPACE(spl_fixpt_u3d19(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1202

dscl_prog_data->ratios.v_scale_ratio = SPL_NAMESPACE(spl_fixpt_u3d19(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1204

dscl_prog_data->ratios.h_scale_ratio_c = SPL_NAMESPACE(spl_fixpt_u3d19(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1206

dscl_prog_data->ratios.v_scale_ratio_c = SPL_NAMESPACE(spl_fixpt_u3d19(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1211

dscl_prog_data->init.h_filter_init_frac =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1213

dscl_prog_data->init.h_filter_init_int =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1215

dscl_prog_data->init.h_filter_init_frac_c =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1217

dscl_prog_data->init.h_filter_init_int_c =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1219

dscl_prog_data->init.v_filter_init_frac =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1221

dscl_prog_data->init.v_filter_init_int =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1223

dscl_prog_data->init.v_filter_init_frac_c =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1225

dscl_prog_data->init.v_filter_init_int_c =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1229

dscl_prog_data->init.v_filter_init_bot_frac = SPL_NAMESPACE(spl_fixpt_u0d19(bot)) << 5;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1230

dscl_prog_data->init.v_filter_init_bot_int = spl_fixpt_floor(bot);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1232

dscl_prog_data->init.v_filter_init_bot_frac_c = SPL_NAMESPACE(spl_fixpt_u0d19(bot)) << 5;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1233

dscl_prog_data->init.v_filter_init_bot_int_c = spl_fixpt_floor(bot);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1236

static void spl_set_taps_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1239

dscl_prog_data->taps.v_taps = scl_data->taps.v_taps - 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1240

dscl_prog_data->taps.h_taps = scl_data->taps.h_taps - 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1241

dscl_prog_data->taps.v_taps_c = scl_data->taps.v_taps_c - 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1242

dscl_prog_data->taps.h_taps_c = scl_data->taps.h_taps_c - 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1249

struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1253

struct scl_black_color *scl_black_color = &dscl_prog_data->scl_black_color;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1258

dscl_prog_data->recout = spl_scratch->scl_data.recout;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1260

dscl_prog_data->mpc_size.width = spl_scratch->scl_data.h_active;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1261

dscl_prog_data->mpc_size.height = spl_scratch->scl_data.v_active;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1264

dscl_prog_data->dscl_mode = spl_get_dscl_mode(spl_in, data, enable_isharp,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1271

spl_set_manual_ratio_init_data(dscl_prog_data, data);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1274

spl_set_taps_data(dscl_prog_data, data);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1276

dscl_prog_data->viewport = spl_scratch->scl_data.viewport;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1278

dscl_prog_data->viewport_c = spl_scratch->scl_data.viewport_c;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1280

SPL_NAMESPACE(spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h));

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1284

static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t sdr_white_level_nits)

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1314

&dscl_prog_data->easf_matrix_c0));

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1317

&dscl_prog_data->easf_matrix_c1));

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1320

&dscl_prog_data->easf_matrix_c2));

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1321

dscl_prog_data->easf_matrix_c3 = 0x0; // fp1.5.10, C3 coefficient

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1330

struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1332

dscl_prog_data->easf_v_en = true;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1333

dscl_prog_data->easf_v_ring = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1334

dscl_prog_data->easf_v_sharp_factor = 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1335

dscl_prog_data->easf_v_bf1_en = 1; // 1-bit, BF1 calculation enable, 0=disable, 1=enable

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1336

dscl_prog_data->easf_v_bf2_mode = 0xF; // 4-bit, BF2 calculation mode

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1338

dscl_prog_data->easf_v_bf3_mode = SPL_NAMESPACE(spl_get_v_bf3_mode(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1341

dscl_prog_data->easf_v_ringest_3tap_dntilt_uptilt =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1345

dscl_prog_data->easf_v_ringest_3tap_uptilt_max =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1349

dscl_prog_data->easf_v_ringest_3tap_dntilt_slope =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1353

dscl_prog_data->easf_v_ringest_3tap_uptilt1_slope =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1357

dscl_prog_data->easf_v_ringest_3tap_uptilt2_slope =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1361

dscl_prog_data->easf_v_ringest_3tap_uptilt2_offset =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1365

dscl_prog_data->easf_v_ringest_eventap_reduceg1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1369

dscl_prog_data->easf_v_ringest_eventap_reduceg2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1373

dscl_prog_data->easf_v_ringest_eventap_gain1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1377

dscl_prog_data->easf_v_ringest_eventap_gain2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1380

dscl_prog_data->easf_v_bf_maxa = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1381

dscl_prog_data->easf_v_bf_maxb = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1382

dscl_prog_data->easf_v_bf_mina = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1383

dscl_prog_data->easf_v_bf_minb = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1385

dscl_prog_data->easf_v_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1386

dscl_prog_data->easf_v_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1387

dscl_prog_data->easf_v_bf2_roc_gain = 4; // U2.2, Rate Of Change control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1389

dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1390

dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1391

dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1392

dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1393

dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1394

dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1395

dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1396

dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1397

dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1398

dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1399

dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1400

dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = 0x7C8; // S7.3, BF1 Slope PWL Segment 3 = -56

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1401

dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1402

dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1403

dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = 0x7D0; // S7.3, BF1 Slope PWL Segment 4 = -48

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1404

dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1405

dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1406

dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = 0x710; // S7.3, BF1 Slope PWL Segment 5 = -240

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1407

dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1408

dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1409

dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = 0x760; // S7.3, BF1 Slope PWL Segment 6 = -160

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1410

dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1411

dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1413

dscl_prog_data->easf_v_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1414

dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1415

dscl_prog_data->easf_v_bf3_pwl_slope_set0 = 0x12C5; // FP1.6.6, BF3 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1416

dscl_prog_data->easf_v_bf3_pwl_in_set1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1418

dscl_prog_data->easf_v_bf3_pwl_base_set1 = 62; // S0.6, BF3 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1419

dscl_prog_data->easf_v_bf3_pwl_slope_set1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1421

dscl_prog_data->easf_v_bf3_pwl_in_set2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1423

dscl_prog_data->easf_v_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1424

dscl_prog_data->easf_v_bf3_pwl_slope_set2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1426

dscl_prog_data->easf_v_bf3_pwl_in_set3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1428

dscl_prog_data->easf_v_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1429

dscl_prog_data->easf_v_bf3_pwl_slope_set3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1431

dscl_prog_data->easf_v_bf3_pwl_in_set4 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1433

dscl_prog_data->easf_v_bf3_pwl_base_set4 = 0x4E; // S0.6, BF3 Base PWL Segment 4 = -50

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1434

dscl_prog_data->easf_v_bf3_pwl_slope_set4 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1436

dscl_prog_data->easf_v_bf3_pwl_in_set5 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1438

dscl_prog_data->easf_v_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1440

dscl_prog_data->easf_v_bf2_flat1_gain = 13; // U1.3, BF2 Flat1 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1441

dscl_prog_data->easf_v_bf2_flat2_gain = 15; // U4.0, BF2 Flat2 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1442

dscl_prog_data->easf_v_bf2_roc_gain = 14; // U2.2, Rate Of Change control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1444

dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x440; // S0.10, BF1 PWL Segment 0 = -960

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1445

dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1446

dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 2; // S7.3, BF1 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1447

dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7C4; // S0.10, BF1 PWL Segment 1 = -60

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1448

dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1449

dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 109; // S7.3, BF1 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1450

dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1451

dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1452

dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1453

dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 48; // S0.10, BF1 PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1454

dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1455

dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = 0x7ED; // S7.3, BF1 Slope PWL Segment 3 = -19

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1456

dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 96; // S0.10, BF1 PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1457

dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1458

dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = 0x7F0; // S7.3, BF1 Slope PWL Segment 4 = -16

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1459

dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 144; // S0.10, BF1 PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1460

dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1461

dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = 0x7B0; // S7.3, BF1 Slope PWL Segment 5 = -80

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1462

dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 192; // S0.10, BF1 PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1463

dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1464

dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = 0x7CB; // S7.3, BF1 Slope PWL Segment 6 = -53

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1465

dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 240; // S0.10, BF1 PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1466

dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1468

dscl_prog_data->easf_v_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1469

dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1470

dscl_prog_data->easf_v_bf3_pwl_slope_set0 = 0x0000; // FP1.6.6, BF3 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1471

dscl_prog_data->easf_v_bf3_pwl_in_set1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1473

dscl_prog_data->easf_v_bf3_pwl_base_set1 = 63; // S0.6, BF3 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1474

dscl_prog_data->easf_v_bf3_pwl_slope_set1 = 0x1896; // FP1.6.6, BF3 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1475

dscl_prog_data->easf_v_bf3_pwl_in_set2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1477

dscl_prog_data->easf_v_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1478

dscl_prog_data->easf_v_bf3_pwl_slope_set2 = 0x1810; // FP1.6.6, BF3 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1479

dscl_prog_data->easf_v_bf3_pwl_in_set3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1481

dscl_prog_data->easf_v_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1482

dscl_prog_data->easf_v_bf3_pwl_slope_set3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1484

dscl_prog_data->easf_v_bf3_pwl_in_set4 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1486

dscl_prog_data->easf_v_bf3_pwl_base_set4 = 0x44; // S0.6, BF3 Base PWL Segment 4 = -60

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1487

dscl_prog_data->easf_v_bf3_pwl_slope_set4 = 0x1760; // FP1.6.6, BF3 Slope PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1488

dscl_prog_data->easf_v_bf3_pwl_in_set5 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1490

dscl_prog_data->easf_v_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1493

dscl_prog_data->easf_v_en = false;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1496

dscl_prog_data->easf_h_en = true;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1497

dscl_prog_data->easf_h_ring = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1498

dscl_prog_data->easf_h_sharp_factor = 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1499

dscl_prog_data->easf_h_bf1_en =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1501

dscl_prog_data->easf_h_bf2_mode =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1504

dscl_prog_data->easf_h_bf3_mode = SPL_NAMESPACE(spl_get_h_bf3_mode(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1507

dscl_prog_data->easf_h_ringest_eventap_reduceg1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1511

dscl_prog_data->easf_h_ringest_eventap_reduceg2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1515

dscl_prog_data->easf_h_ringest_eventap_gain1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1519

dscl_prog_data->easf_h_ringest_eventap_gain2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1522

dscl_prog_data->easf_h_bf_maxa = 63; //Horz Max BF value A in U0.6 format.Selected if H_FCNTL==0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1523

dscl_prog_data->easf_h_bf_maxb = 63; //Horz Max BF value B in U0.6 format.Selected if H_FCNTL==1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1524

dscl_prog_data->easf_h_bf_mina = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1525

dscl_prog_data->easf_h_bf_minb = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1527

dscl_prog_data->easf_h_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1528

dscl_prog_data->easf_h_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1529

dscl_prog_data->easf_h_bf2_roc_gain = 4; // U2.2, Rate Of Change control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1531

dscl_prog_data->easf_h_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1532

dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1533

dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1534

dscl_prog_data->easf_h_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1535

dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1536

dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1537

dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1538

dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1539

dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1540

dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1541

dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1542

dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = 0x7C8; // S7.3, BF1 Slope PWL Segment 3 = -56

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1543

dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1544

dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1545

dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = 0x7D0; // S7.3, BF1 Slope PWL Segment 4 = -48

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1546

dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1547

dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1548

dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = 0x710; // S7.3, BF1 Slope PWL Segment 5 = -240

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1549

dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1550

dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1551

dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = 0x760; // S7.3, BF1 Slope PWL Segment 6 = -160

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1552

dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1553

dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1555

dscl_prog_data->easf_h_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1556

dscl_prog_data->easf_h_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1557

dscl_prog_data->easf_h_bf3_pwl_slope_set0 = 0x12C5; // FP1.6.6, BF3 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1558

dscl_prog_data->easf_h_bf3_pwl_in_set1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1560

dscl_prog_data->easf_h_bf3_pwl_base_set1 = 62; // S0.6, BF3 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1561

dscl_prog_data->easf_h_bf3_pwl_slope_set1 = 0x13B8; // FP1.6.6, BF3 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1562

dscl_prog_data->easf_h_bf3_pwl_in_set2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1564

dscl_prog_data->easf_h_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1565

dscl_prog_data->easf_h_bf3_pwl_slope_set2 = 0x1356; // FP1.6.6, BF3 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1566

dscl_prog_data->easf_h_bf3_pwl_in_set3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1568

dscl_prog_data->easf_h_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1569

dscl_prog_data->easf_h_bf3_pwl_slope_set3 = 0x136B; // FP1.6.6, BF3 Slope PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1570

dscl_prog_data->easf_h_bf3_pwl_in_set4 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1572

dscl_prog_data->easf_h_bf3_pwl_base_set4 = 0x4E; // S0.6, BF3 Base PWL Segment 4 = -50

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1573

dscl_prog_data->easf_h_bf3_pwl_slope_set4 = 0x1200; // FP1.6.6, BF3 Slope PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1574

dscl_prog_data->easf_h_bf3_pwl_in_set5 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1576

dscl_prog_data->easf_h_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1578

dscl_prog_data->easf_h_bf2_flat1_gain = 13; // U1.3, BF2 Flat1 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1579

dscl_prog_data->easf_h_bf2_flat2_gain = 15; // U4.0, BF2 Flat2 Gain control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1580

dscl_prog_data->easf_h_bf2_roc_gain = 14; // U2.2, Rate Of Change control

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1582

dscl_prog_data->easf_h_bf1_pwl_in_seg0 = 0x440; // S0.10, BF1 PWL Segment 0 = -960

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1583

dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1584

dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 2; // S7.3, BF1 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1585

dscl_prog_data->easf_h_bf1_pwl_in_seg1 = 0x7C4; // S0.10, BF1 PWL Segment 1 = -60

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1586

dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1587

dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 109; // S7.3, BF1 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1588

dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1589

dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1590

dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1591

dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 48; // S0.10, BF1 PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1592

dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1593

dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = 0x7ED; // S7.3, BF1 Slope PWL Segment 3 = -19

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1594

dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 96; // S0.10, BF1 PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1595

dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1596

dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = 0x7F0; // S7.3, BF1 Slope PWL Segment 4 = -16

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1597

dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 144; // S0.10, BF1 PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1598

dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1599

dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = 0x7B0; // S7.3, BF1 Slope PWL Segment 5 = -80

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1600

dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 192; // S0.10, BF1 PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1601

dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1602

dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = 0x7CB; // S7.3, BF1 Slope PWL Segment 6 = -53

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1603

dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 240; // S0.10, BF1 PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1604

dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1606

dscl_prog_data->easf_h_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1607

dscl_prog_data->easf_h_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1608

dscl_prog_data->easf_h_bf3_pwl_slope_set0 = 0x0000; // FP1.6.6, BF3 Slope PWL Segment 0

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1609

dscl_prog_data->easf_h_bf3_pwl_in_set1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1611

dscl_prog_data->easf_h_bf3_pwl_base_set1 = 63; // S0.6, BF3 Base PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1612

dscl_prog_data->easf_h_bf3_pwl_slope_set1 = 0x1896; // FP1.6.6, BF3 Slope PWL Segment 1

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1613

dscl_prog_data->easf_h_bf3_pwl_in_set2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1615

dscl_prog_data->easf_h_bf3_pwl_base_set2 = 20; // S0.6, BF3 Base PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1616

dscl_prog_data->easf_h_bf3_pwl_slope_set2 = 0x1810; // FP1.6.6, BF3 Slope PWL Segment 2

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1617

dscl_prog_data->easf_h_bf3_pwl_in_set3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1619

dscl_prog_data->easf_h_bf3_pwl_base_set3 = 0; // S0.6, BF3 Base PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1620

dscl_prog_data->easf_h_bf3_pwl_slope_set3 = 0x1878; // FP1.6.6, BF3 Slope PWL Segment 3

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1621

dscl_prog_data->easf_h_bf3_pwl_in_set4 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1623

dscl_prog_data->easf_h_bf3_pwl_base_set4 = 0x44; // S0.6, BF3 Base PWL Segment 4 = -60

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1624

dscl_prog_data->easf_h_bf3_pwl_slope_set4 = 0x1760; // FP1.6.6, BF3 Slope PWL Segment 4

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1625

dscl_prog_data->easf_h_bf3_pwl_in_set5 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1627

dscl_prog_data->easf_h_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1630

dscl_prog_data->easf_h_en = false;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1633

dscl_prog_data->easf_ltonl_en = 1; // Linear input

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1636

spl_calculate_c0_c3_hdr(dscl_prog_data, sdr_white_level_nits);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1638

dscl_prog_data->easf_matrix_c0 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1640

dscl_prog_data->easf_matrix_c1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1642

dscl_prog_data->easf_matrix_c2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1644

dscl_prog_data->easf_matrix_c3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1648

dscl_prog_data->easf_ltonl_en = 0; // Non-Linear input

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1649

dscl_prog_data->easf_matrix_c0 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1651

dscl_prog_data->easf_matrix_c1 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1653

dscl_prog_data->easf_matrix_c2 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1655

dscl_prog_data->easf_matrix_c3 =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1660

dscl_prog_data->easf_matrix_mode = 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1666

dscl_prog_data->easf_v_bf3_mode = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1667

dscl_prog_data->easf_h_bf3_mode = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1669

dscl_prog_data->easf_matrix_mode = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1674

static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1683

dscl_prog_data->isharp_noise_det.mode = 3;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1685

dscl_prog_data->isharp_noise_det.mode = 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1687

dscl_prog_data->isharp_noise_det.mode = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1690

static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1698

dscl_prog_data->isharp_en = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1704

memcpy(dscl_prog_data->isharp_delta, SPL_NAMESPACE(spl_get_pregen_filter_isharp_1D_lut(setup)),

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1706

dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1708

dscl_prog_data->isharp_en = 1; // ISHARP_EN

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1711

dscl_prog_data->isharp_noise_det.enable = 1; /* ISHARP_NOISEDET_EN */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1712

spl_set_isharp_noise_det_mode(dscl_prog_data, data); /* ISHARP_NOISEDET_MODE */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1714

dscl_prog_data->isharp_noise_det.enable = 0; // ISHARP_NOISEDET_EN

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1716

dscl_prog_data->isharp_noise_det.uthreshold = 24; // ISHARP_NOISEDET_UTHRE

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1717

dscl_prog_data->isharp_noise_det.dthreshold = 4; // ISHARP_NOISEDET_DTHRE

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1719

dscl_prog_data->isharp_noise_det.pwl_start_in = 3; // ISHARP_NOISEDET_PWL_START_IN

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1720

dscl_prog_data->isharp_noise_det.pwl_end_in = 13; // ISHARP_NOISEDET_PWL_END_IN

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1721

dscl_prog_data->isharp_noise_det.pwl_slope = 1623; // ISHARP_NOISEDET_PWL_SLOPE

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1724

dscl_prog_data->isharp_fmt.mode = 1;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1726

dscl_prog_data->isharp_fmt.mode = 0;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1728

dscl_prog_data->isharp_fmt.norm = 0x3C00; // ISHARP_FMT_NORM

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1729

dscl_prog_data->isharp_lba.mode = 0; // ISHARP_LBA_MODE

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1733

dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1734

dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1735

dscl_prog_data->isharp_lba.slope_seg[0] = 62; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1737

dscl_prog_data->isharp_lba.in_seg[1] = 130; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1738

dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1739

dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1741

dscl_prog_data->isharp_lba.in_seg[2] = 450; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1742

dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1743

dscl_prog_data->isharp_lba.slope_seg[2] = 0x18D; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -115

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1745

dscl_prog_data->isharp_lba.in_seg[3] = 520; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1746

dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1747

dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1749

dscl_prog_data->isharp_lba.in_seg[4] = 520; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1750

dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1751

dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1753

dscl_prog_data->isharp_lba.in_seg[5] = 520; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1754

dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1757

dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1758

dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1759

dscl_prog_data->isharp_lba.slope_seg[0] = 32; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1761

dscl_prog_data->isharp_lba.in_seg[1] = 254; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1762

dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1763

dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1765

dscl_prog_data->isharp_lba.in_seg[2] = 559; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1766

dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1767

dscl_prog_data->isharp_lba.slope_seg[2] = 0x10C; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -244

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1769

dscl_prog_data->isharp_lba.in_seg[3] = 592; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1770

dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1771

dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1773

dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1774

dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1775

dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1777

dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1778

dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1781

dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1782

dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1783

dscl_prog_data->isharp_lba.slope_seg[0] = 40; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1785

dscl_prog_data->isharp_lba.in_seg[1] = 204; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1786

dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1787

dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1789

dscl_prog_data->isharp_lba.in_seg[2] = 818; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1790

dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1791

dscl_prog_data->isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1793

dscl_prog_data->isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1794

dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1795

dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1797

dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1798

dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1799

dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1801

dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1802

dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1807

dscl_prog_data->isharp_nldelta_sclip.enable_p = 0; /* ISHARP_NLDELTA_SCLIP_EN_P */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1808

dscl_prog_data->isharp_nldelta_sclip.pivot_p = 0; /* ISHARP_NLDELTA_SCLIP_PIVOT_P */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1809

dscl_prog_data->isharp_nldelta_sclip.slope_p = 0; /* ISHARP_NLDELTA_SCLIP_SLOPE_P */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1810

dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; /* ISHARP_NLDELTA_SCLIP_EN_N */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1811

dscl_prog_data->isharp_nldelta_sclip.pivot_n = 71; /* ISHARP_NLDELTA_SCLIP_PIVOT_N */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1812

dscl_prog_data->isharp_nldelta_sclip.slope_n = 16; /* ISHARP_NLDELTA_SCLIP_SLOPE_N */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1814

dscl_prog_data->isharp_nldelta_sclip.enable_p = 1; /* ISHARP_NLDELTA_SCLIP_EN_P */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1815

dscl_prog_data->isharp_nldelta_sclip.pivot_p = 70; /* ISHARP_NLDELTA_SCLIP_PIVOT_P */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1816

dscl_prog_data->isharp_nldelta_sclip.slope_p = 24; /* ISHARP_NLDELTA_SCLIP_SLOPE_P */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1817

dscl_prog_data->isharp_nldelta_sclip.enable_n = 1; /* ISHARP_NLDELTA_SCLIP_EN_N */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1818

dscl_prog_data->isharp_nldelta_sclip.pivot_n = 70; /* ISHARP_NLDELTA_SCLIP_PIVOT_N */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1819

dscl_prog_data->isharp_nldelta_sclip.slope_n = 24; /* ISHARP_NLDELTA_SCLIP_SLOPE_N */

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1823

SPL_NAMESPACE(spl_set_blur_scale_data(dscl_prog_data, data));

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1912

spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1927

struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data;

drivers/gpu/drm/amd/display/dc/sspl/dc_spl.c

1932

spl_set_taps_data(dscl_prog_data, data);

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

546

void SPL_NAMESPACE(spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

549

dscl_prog_data->filter_blur_scale_h =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.c

552

dscl_prog_data->filter_blur_scale_v =

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_isharp_filters.h

31

void SPL_NAMESPACE(spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2347

void SPL_NAMESPACE(spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2356

dscl_prog_data->filter_h = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2359

dscl_prog_data->filter_h_c = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2362

dscl_prog_data->filter_h = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2365

dscl_prog_data->filter_h_c = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2369

dscl_prog_data->filter_v = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2372

dscl_prog_data->filter_v_c = SPL_NAMESPACE(spl_dscl_get_easf_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2375

dscl_prog_data->filter_v = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.c

2378

dscl_prog_data->filter_v_c = SPL_NAMESPACE(spl_dscl_get_filter_coeffs_64p(

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_scl_easf_filters.h

16

void SPL_NAMESPACE(spl_set_filters_data(struct dscl_prog_data *dscl_prog_data,

drivers/gpu/drm/amd/display/dc/sspl/dc_spl_types.h

423

struct dscl_prog_data *dscl_prog_data;