drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1009

const struct dsc_enc_caps *single_dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1010

struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1014

dsc_enc_caps->slice_caps.raw |= single_dsc_enc_caps->slice_caps.raw;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1019

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1022

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1025

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1028

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1034

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1040

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1043

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1046

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_3;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1049

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 |= single_dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1055

struct dsc_enc_caps *dsc_enc_caps)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1060

struct dsc_enc_caps single_dsc_enc_caps;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1078

dsc_enc_caps->dsc_version = single_dsc_enc_caps.dsc_version;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1079

dsc_enc_caps->lb_bit_depth = single_dsc_enc_caps.lb_bit_depth;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1080

dsc_enc_caps->is_block_pred_supported = single_dsc_enc_caps.is_block_pred_supported;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1081

dsc_enc_caps->max_slice_width = single_dsc_enc_caps.max_slice_width;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1082

dsc_enc_caps->bpp_increment_div = single_dsc_enc_caps.bpp_increment_div;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1083

dsc_enc_caps->color_formats.raw = single_dsc_enc_caps.color_formats.raw;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1084

dsc_enc_caps->color_depth.raw = single_dsc_enc_caps.color_depth.raw;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1090

dsc_enc_caps->max_total_throughput_mps =

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1095

build_dsc_enc_combined_slice_caps(&single_dsc_enc_caps, dsc_enc_caps, max_odm_combine_factor);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1105

const struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1111

max_dispclk_khz = dsc_enc_caps->max_total_throughput_mps * 1000;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1121

if (max_dispclk_khz == 0 || dsc_enc_caps->max_slice_width == 0)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1132

dsc_enc_caps->max_slice_width))); // slice width

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1137

struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1140

memset(dsc_enc_caps, 0, sizeof(struct dsc_enc_caps));

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1147

dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1149

build_dsc_enc_caps(dsc, dsc_enc_caps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1158

const struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1160

struct dsc_enc_caps *dsc_common_caps)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1165

memset(dsc_common_caps, 0, sizeof(struct dsc_enc_caps));

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1167

dsc_common_caps->dsc_version = min(dsc_sink_caps->dsc_version, dsc_enc_caps->dsc_version);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1172

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_1 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_1;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1174

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_2 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_2;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1176

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_4 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_4;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1178

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_8 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_8;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1180

dsc_sink_caps->slice_caps1.bits.NUM_SLICES_12 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_12;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1182

dsc_sink_caps->slice_caps2.bits.NUM_SLICES_16 && dsc_enc_caps->slice_caps.bits.NUM_SLICES_16;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1187

dsc_common_caps->lb_bit_depth = min(dsc_sink_caps->lb_bit_depth, dsc_enc_caps->lb_bit_depth);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1192

dsc_sink_caps->is_block_pred_supported && dsc_enc_caps->is_block_pred_supported;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1194

dsc_common_caps->color_formats.raw = dsc_sink_caps->color_formats.raw & dsc_enc_caps->color_formats.raw;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1198

dsc_common_caps->color_depth.raw = dsc_sink_caps->color_depth.raw & dsc_enc_caps->color_depth.raw;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1216

dsc_common_caps->max_total_throughput_mps = min(total_sink_throughput, dsc_enc_caps->max_total_throughput_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1218

dsc_common_caps->max_slice_width = min(dsc_sink_caps->max_slice_width, dsc_enc_caps->max_slice_width);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1222

dsc_common_caps->bpp_increment_div = min(dsc_sink_caps->bpp_increment_div, dsc_enc_caps->bpp_increment_div);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1302

const struct dsc_enc_caps *dsc_caps)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1454

const struct dsc_enc_caps *dsc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1533

const struct dsc_enc_caps *dsc_common_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1729

const struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1737

struct dsc_enc_caps dsc_common_caps;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

1767

is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2002

struct dsc_enc_caps dsc_enc_caps;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2004

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2006

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

2009

&dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

317

const struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

324

const struct dsc_enc_caps *dsc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

338

struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

343

const struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

345

struct dsc_enc_caps *dsc_common_caps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

349

const struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

365

const struct dsc_enc_caps *dsc_caps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

621

const struct dsc_enc_caps *dsc_common_caps)

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

938

struct dsc_enc_caps dsc_enc_caps;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

939

struct dsc_enc_caps dsc_common_caps;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

947

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

949

min_dsc_slice_count = get_min_dsc_slice_count_for_odm(dsc, &dsc_enc_caps, timing);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

951

is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, &dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

955

is_dsc_possible = setup_dsc_config(dsc_sink_caps, &dsc_enc_caps, 0, timing,

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

968

struct dsc_enc_caps dsc_enc_caps;

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

970

get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

973

DC_LOG_DSC("\tdsc_version 0x%x", dsc_enc_caps.dsc_version);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

974

DC_LOG_DSC("\tslice_caps 0x%x", dsc_enc_caps.slice_caps.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

975

DC_LOG_DSC("\tlb_bit_depth %d", dsc_enc_caps.lb_bit_depth);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

976

DC_LOG_DSC("\tis_block_pred_supported %d", dsc_enc_caps.is_block_pred_supported);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

977

DC_LOG_DSC("\tcolor_formats 0x%x", dsc_enc_caps.color_formats.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

978

DC_LOG_DSC("\tcolor_depth 0x%x", dsc_enc_caps.color_depth.raw);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

979

DC_LOG_DSC("\tmax_total_throughput_mps %d", dsc_enc_caps.max_total_throughput_mps);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

980

DC_LOG_DSC("\tmax_slice_width %d", dsc_enc_caps.max_slice_width);

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

981

DC_LOG_DSC("\tbpp_increment_div %d", dsc_enc_caps.bpp_increment_div);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

100

dsc_enc_caps->color_formats.bits.RGB = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

101

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

102

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

103

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

104

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

106

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

107

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

108

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

115

dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

121

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

122

dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

123

dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

130

dsc_enc_caps->slice_caps.bits.NUM_SLICES_12 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

131

dsc_enc_caps->slice_caps.bits.NUM_SLICES_16 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

132

dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 4;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

135

dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

136

dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

88

void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

90

dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

92

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

93

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

94

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

95

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

97

dsc_enc_caps->lb_bit_depth = 13;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

98

dsc_enc_caps->is_block_pred_supported = true;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

601

void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps,

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

116

void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

118

dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

120

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

121

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

122

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

123

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

125

dsc_enc_caps->lb_bit_depth = 13;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

126

dsc_enc_caps->is_block_pred_supported = true;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

128

dsc_enc_caps->color_formats.bits.RGB = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

129

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

130

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

131

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

132

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

134

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

135

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

136

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

138

dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

140

dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

141

dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */

drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c

31

static void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

17

static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

66

static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

68

dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

70

dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

71

dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

72

dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

73

dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

75

dsc_enc_caps->lb_bit_depth = 13;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

76

dsc_enc_caps->is_block_pred_supported = true;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

78

dsc_enc_caps->color_formats.bits.RGB = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

79

dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

80

dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

81

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

82

dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

84

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

85

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

86

dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

87

dsc_enc_caps->max_total_throughput_mps = max_dscclk_khz * 3 / 1000;

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

89

dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

90

dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

115

void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

127

void (*dsc_get_single_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, unsigned int max_dscclk_khz);