dsaf_write_dev
dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl);
dsaf_write_dev(drv, GMAC_TX_LOOP_PKT_PRI_REG, tx_loop_pkt_pri);
dsaf_write_dev(drv, GMAC_PAUSE_EN_REG, pause_en);
dsaf_write_dev(drv, GMAC_STATION_ADDR_LOW_2_REG, low_val);
dsaf_write_dev(drv, GMAC_STATION_ADDR_HIGH_2_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG, 0);
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG, 0);
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG, 0);
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG, 0);
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, 0);
dsaf_write_dev(dsaf_dev, DSAF_PFC_EN_0_REG + mac_id * 4, tc_en);
dsaf_write_dev(dsaf_dev, DSAF_CFG_0_REG, o_dsaf_cfg);
dsaf_write_dev(dsaf_dev, reg, tc_cfg);
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(dsaf_dev, reg, o_sbm_bp_cfg);
dsaf_write_dev(
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_L_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MATCH_CFG_H_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_LOW_0_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_HIGH_0_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_4_0_REG, mcast_cfg4);
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_3_0_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_2_0_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_1_0_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_MCAST_CFG_0_0_REG,
dsaf_write_dev(dsaf_dev, DSAF_TBL_TCAM_UCAST_CFG_0_REG, ucast_cfg1);
dsaf_write_dev(dsaf_dev, DSAF_TBL_LIN_CFG_0_REG, tbl_line);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_DFX_CTRL_0_REG, o_tbl_ctrl);
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_MSK_0_REG, msk_set);
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev,
dsaf_write_dev(dsaf_dev, DSAF_TBL_INT_SRC_0_REG, int_src);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(dsaf_dev, DSAF_TBL_PUL_0_REG, o_tbl_pul);
dsaf_write_dev(ppe_cb, PPEV2_VLAN_STRIP_EN_REG, en);
dsaf_write_dev(ppe_common, PPE_COM_CFG_QID_MODE_REG, qid_mod);
dsaf_write_dev(ppe_cb, PPE_CFG_XGE_MODE_REG, mode);
dsaf_write_dev(ppe_cb, PPEV2_RSS_KEY_REG + key_item * 0x4,
dsaf_write_dev(ppe_cb, PPE_RINT_REG, clr_vlue);
dsaf_write_dev(ppe_cb, PPE_INTEN_REG, msk_vlue & vld_msk);
dsaf_write_dev(ppe_cb, PPE_CFG_PAUSE_IDLE_CNT_REG, 0);
dsaf_write_dev(ppe_cb, PPE_CFG_MAX_FRAME_LEN_REG,
dsaf_write_dev(
dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,
dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,
dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, 1);
dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, 1);
dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, 1);
dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, 1);
dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
dsaf_write_dev(q, RCBV2_TX_RING_INT_STS_REG, 1);
dsaf_write_dev(q, RCBV2_RX_RING_INT_STS_REG, 1);
dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);
dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);
dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG,
dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,
dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,
dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,
dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,
dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,
dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG,
dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG,
dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG,
dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG,
dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4,
dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG,
dsaf_write_dev(rcb_common,
dsaf_write_dev(rcb_common,
dsaf_write_dev(rcb_common,
dsaf_write_dev(rcb_common,
dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue);
dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue);
dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue);
dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue);
dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue);
dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue);
dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue);
dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2);
dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue);
dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue);
dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,
dsaf_write_dev(rcb_common, RCB_COM_CFG_FNA_REG, 0x0);
dsaf_write_dev(rcb_common, RCB_COM_CFG_FA_REG, 0x1);
dsaf_write_dev(rcb_common, reg, coalesced_frames);
dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4,
dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1);
dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1);
dsaf_write_dev(mac_drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG, val);
dsaf_write_dev(drv, XGMAC_PMA_FEC_CONTROL_REG, origin);
dsaf_write_dev(drv, XGMAC_INT_STATUS_REG, clr_vlue);
dsaf_write_dev(drv, XGMAC_INT_ENABLE_REG, msk_vlue);
dsaf_write_dev(drv, XGMAC_MAC_CONTROL_REG, origin);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_CTRL_REG, origin);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_L_REG, low_val);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_LOCAL_MAC_H_REG, high_val);
dsaf_write_dev(drv, XGMAC_MAC_PAUSE_TIME_REG, enable);
dsaf_write_dev(drv, XGMAC_MAC_MAX_PKT_SIZE_REG, newval);