dsaf_set_field
dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_VLAN_M,
dsaf_set_field(mac_key->low.bits.port_vlan, DSAF_TBL_TCAM_KEY_PORT_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_COM_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC0_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG0_VC1_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC4_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG1_TC0_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_SET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAF_SBM_CFG2_RESET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_COM_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC0_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG0_VC1_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC4_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG1_TC0_MAX_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_SET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg, DSAFV2_SBM_CFG2_RESET_BUF_NUM_M,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(o_sbm_bp_cfg,
dsaf_set_field(voq_bp_all_thrd,
dsaf_set_field(voq_bp_all_thrd,
dsaf_set_field(voq_bp_all_thrd,
dsaf_set_field(voq_bp_all_thrd,
dsaf_set_field(mcast_cfg4, DSAF_TBL_MCAST_CFG4_VM128_112_M,
dsaf_set_field(ucast_cfg1, DSAF_TBL_UCAST_CFG1_OUT_PORT_M,
dsaf_set_field(tbl_line, DSAF_TBL_LINE_CFG_OUT_PORT_M,
dsaf_set_field(value, DSAF_LED_SPEED_M,
dsaf_set_field(origin, 1ull << 10, 10, en);
dsaf_set_field(qid_mod, PPE_CFG_QID_MODE_DEF_QID_M,
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N0_M,
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N1_M,
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N2_M,
dsaf_set_field(reg_value, PPEV2_CFG_RSS_TBL_4N3_M,
dsaf_set_field((origin), (1ull << (shift)), (shift), (val))
dsaf_set_field(origin, mask, shift, val);
dsaf_set_field(val, XGMAC_LF_RF_INSERT_M, XGMAC_LF_RF_INSERT_S, 0);