dsaf_set_dev_field
dsaf_set_dev_field(drv, GMAC_FC_TX_TIMER_REG, GMAC_FC_TX_TIMER_M,
dsaf_set_dev_field(drv, GMAC_MAX_FRM_SIZE_REG, GMAC_MAX_FRM_SIZE_M,
dsaf_set_dev_field(drv, GAMC_RX_MAX_FRAME, GMAC_MAX_FRM_SIZE_M,
dsaf_set_dev_field(
dsaf_set_dev_field(
dsaf_set_dev_field(
dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev, reg,
dsaf_set_dev_field(dsaf_dev,
dsaf_set_dev_field(dsaf_dev,
dsaf_set_dev_field(dsaf_dev,
dsaf_set_dev_field(dsaf_dev,
dsaf_set_dev_field(dsaf_dev,
dsaf_set_dev_field(dsaf_dev,
dsaf_set_dev_field(dsaf_dev, DSAF_TBL_TCAM_ADDR_0_REG,
dsaf_set_dev_field(dsaf_dev, DSAF_TBL_LINE_ADDR_0_REG,
dsaf_set_dev_field(ppe_cb, PPE_CFG_PRO_CHECK_EN_REG,
dsaf_set_dev_field(ppe_common, PPE_COM_CFG_QID_MODE_REG,
dsaf_set_dev_field(mac_drv, XGMAC_MAC_TX_LF_RF_CONTROL_REG,