dwc_phy_write_mask
dwc_phy_write_mask(isys, id, CORE_DIG_RW_COMMON_7, 0, 0, 9);
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_7,
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_7,
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_8, 80, 0, 7);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_0, 191, 0, 9);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_7, 34, 7, 12);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_1, 38, 8, 15);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 4, 12, 15);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 2, 10, 11);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 1, 8, 8);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 38, 0, 7);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_2, 1, 9, 9);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_4, 10, 0, 9);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_6, 20, 0, 9);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_7, 19, 0, 6);
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_3,
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_1,
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_5,
dwc_phy_write_mask(isys, id, PPI_RW_DDLCAL_CFG_5,
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val,
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 6, 8, 11);
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_2,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id, CORE_DIG_RW_COMMON_6, 1, 0, 2);
dwc_phy_write_mask(isys, id, CORE_DIG_RW_COMMON_6, 1, 3, 5);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val, 1, 1);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), !val, 3, 3);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val, 1, 1);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val, 3, 3);
dwc_phy_write_mask(isys, id, reg,
dwc_phy_write_mask(isys, id, CORE_DIG_RW_COMMON_0, 1,
dwc_phy_write_mask(isys, id, reg, 3, 3, 4);
dwc_phy_write_mask(isys, id, reg, val, 3, 4);
dwc_phy_write_mask(isys, id, reg, 3, 3, 4);
dwc_phy_write_mask(isys, id, CORE_DIG_DLANE_CLK_RW_HS_RX_0, 28, 0, 7);
dwc_phy_write_mask(isys, id, CORE_DIG_DLANE_CLK_RW_HS_RX_7, 6, 0, 7);
dwc_phy_write_mask(isys, id, reg + (j * 0x400),
dwc_phy_write_mask(isys, id, reg + (i * 0x400),
dwc_phy_write_mask(isys, id, reg + (i * 0x400),
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 1, 13, 13);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 7, 9, 12);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 1, 12, 15);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 0, 0, 0);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 16, 0, 7);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 2, 0, 2);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val,
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 150, 0, 15);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 0, 0, 7);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 1, 8, 15);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 2, 0, 7);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val,
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 0, 13, 13);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 0, 15, 15);
dwc_phy_write_mask(isys, id, reg + (i * 0x400),
dwc_phy_write_mask(isys, id, CORE_DIG_DLANE_CLK_RW_LP_0, 1, 12, 15);
dwc_phy_write_mask(isys, id, CORE_DIG_DLANE_CLK_RW_LP_2, 0, 0, 0);
dwc_phy_write_mask(isys, id, CORE_DIG_COMMON_RW_DESKEW_FINE_MEM,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_9,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_9,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_9,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_15,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_15,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_15,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_8,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7,
dwc_phy_write_mask(isys, id, CORE_DIG_RW_COMMON_7, val, 0, 9);
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_7, 104, 0, 7);
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_8, 16, 0, 7);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 6, 8, 11);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 1, 0, 0);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), val, 1, 1);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 38, 0, 15);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 38, 0, 15);
dwc_phy_write_mask(isys, id, reg + (i * 0x400), 10, 0, 15);
dwc_phy_write_mask(isys, id, reg, coarse_target, 0, 15);
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id,
dwc_phy_write_mask(isys, id, reg, 1, 6, 8);
dwc_phy_write_mask(isys, id, reg, 1, 3, 5);
dwc_phy_write_mask(isys, id, reg, 2, 0, 2);
dwc_phy_write_mask(isys, id, reg + 0x400 * i,
dwc_phy_write_mask(isys, id, reg + 0x400 * i,
dwc_phy_write_mask(isys, id, reg + 0x400 * i,
dwc_phy_write_mask(isys, id, reg + 0x400 * i, 2, 12, 15);
dwc_phy_write_mask(isys, id, reg + 0x400 * i, 0, 0, 0);
dwc_phy_write_mask(isys, id, reg + 0x400 * i, 12, 2, 6);
dwc_phy_write_mask(isys, id, reg, 4U, 0, 2);
dwc_phy_write_mask(isys, id, reg, 2U, 3, 4);
dwc_phy_write_mask(isys, id, reg, 0U, 3, 4);
dwc_phy_write_mask(isys, id, reg, cap_prog, 10, 12);
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_10, 48, 0, 7);
dwc_phy_write_mask(isys, id, CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_2,
dwc_phy_write_mask(isys, id, CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_0,
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_STARTUP_1_1,
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_2, 5, 0, 7);
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_2, 0x45,
dwc_phy_write_mask(isys, id, PPI_STARTUP_RW_COMMON_DPHY_6, 39, 0, 7);
dwc_phy_write_mask(isys, id, PPI_CALIBCTRL_RW_COMMON_BG_0, 500, 0, 8);
dwc_phy_write_mask(isys, id, PPI_RW_TERMCAL_CFG_0, 38, 0, 6);
dwc_phy_write_mask(isys, id, PPI_RW_OFFSETCAL_CFG_0, 7, 0, 4);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_TIMEBASE, 153, 0, 9);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_NREF, 800, 0, 10);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_NREF_RANGE, 27, 0, 4);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_TWAIT_CONFIG, 47, 0, 8);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_TWAIT_CONFIG, 127, 9, 15);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_VT_CONFIG, 47, 7, 15);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_VT_CONFIG, 27, 2, 6);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_VT_CONFIG, 3, 0, 1);
dwc_phy_write_mask(isys, id, PPI_RW_LPDCOCAL_COARSE_CFG, 1, 0, 1);
dwc_phy_write_mask(isys, id, PPI_RW_COMMON_CFG, 3, 0, 1);
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_1,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_3,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_0,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_6,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_7,
dwc_phy_write_mask(isys, id, CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_5,