drivers/gpu/drm/amd/amdgpu/atombios_dp.c

482

drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

535

drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

550

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

553

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

557

drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

563

drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

567

drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

574

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

587

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3059

ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

792

wret = drm_dp_dpcd_writeb(&aconnector->dm_dp_aux.aux,

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

162

err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

167

err = drm_dp_dpcd_writeb(&anx6345->aux, DP_DOWNSPREAD_CTRL, 0);

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

675

err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

680

err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

128

ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

136

ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

144

ret = drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

173

ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

177

ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

224

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

281

retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

345

retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

686

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

695

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

826

ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1247

drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1278

drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

808

drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

848

drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

989

drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/ite-it6505.c

645

ret = drm_dp_dpcd_writeb(&it6505->aux, offset, datain);

drivers/gpu/drm/bridge/synopsys/dw-dp.c

714

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/tc358767.c

1174

ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);

drivers/gpu/drm/bridge/tc358767.c

1311

ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

1135

drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,

drivers/gpu/drm/display/drm_dp_helper.c

3155

int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, val);

drivers/gpu/drm/display/drm_dp_helper.c

509

drm_dp_dpcd_writeb(aux,

drivers/gpu/drm/display/drm_dp_helper.c

524

drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,

drivers/gpu/drm/display/drm_dp_helper.c

883

err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);

drivers/gpu/drm/display/drm_dp_helper.c

921

err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);

drivers/gpu/drm/i915/display/intel_alpm.c

506

drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, val);

drivers/gpu/drm/i915/display/intel_alpm.c

642

drm_dp_dpcd_writeb(aux, DP_RECEIVER_ALPM_STATUS, val);

drivers/gpu/drm/i915/display/intel_ddi.c

2325

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/i915/display/intel_ddi.c

2341

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION,

drivers/gpu/drm/i915/display/intel_ddi.c

2347

drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS,

drivers/gpu/drm/i915/display/intel_dp.c

3843

return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, val);

drivers/gpu/drm/i915/display/intel_dp.c

4068

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

drivers/gpu/drm/i915/display/intel_dp.c

4082

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

drivers/gpu/drm/i915/display/intel_dp.c

4361

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/i915/display/intel_dp.c

4367

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/i915/display/intel_dp.c

4519

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

4555

if (drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

5812

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

341

drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1222

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1674

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1860

drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

785

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

786

drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);

drivers/gpu/drm/i915/display/intel_dp_test.c

205

if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,

drivers/gpu/drm/i915/display/intel_dp_test.c

394

status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);

drivers/gpu/drm/i915/display/intel_psr.c

2427

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0);

drivers/gpu/drm/i915/display/intel_psr.c

2430

drm_dp_dpcd_writeb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_psr.c

3539

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_psr.c

3895

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val);

drivers/gpu/drm/i915/display/intel_psr.c

3956

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status);

drivers/gpu/drm/i915/display/intel_psr.c

819

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG3, panel_replay_config_3);

drivers/gpu/drm/i915/display/intel_psr.c

846

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

drivers/gpu/drm/i915/display/intel_psr.c

849

drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val);

drivers/gpu/drm/i915/display/intel_psr.c

862

drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/i915/display/intel_psr.c

873

drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,

drivers/gpu/drm/mediatek/mtk_dp.c

1378

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);

drivers/gpu/drm/mediatek/mtk_dp.c

1382

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D3);

drivers/gpu/drm/mediatek/mtk_dp.c

1562

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_LANE0_SET + lane,

drivers/gpu/drm/mediatek/mtk_dp.c

1595

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, aux_offset);

drivers/gpu/drm/mediatek/mtk_dp.c

1603

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, target_link_rate);

drivers/gpu/drm/mediatek/mtk_dp.c

1604

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET,

drivers/gpu/drm/mediatek/mtk_dp.c

1608

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/mediatek/mtk_dp.c

1687

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/mediatek/mtk_dp.c

1723

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/mediatek/mtk_dp.c

1732

drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/mediatek/mtk_dp.c

1784

ret = drm_dp_dpcd_writeb(&mtk_dp->aux,

drivers/gpu/drm/msm/dp/dp_ctrl.c

1393

ret = drm_dp_dpcd_writeb(ctrl->aux, reg, buf);

drivers/gpu/drm/msm/dp/dp_ctrl.c

186

err = drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, lane_count);

drivers/gpu/drm/msm/dp/dp_ctrl.c

192

err = drm_dp_dpcd_writeb(aux, DP_LINK_RATE_SET, link->rate_set);

drivers/gpu/drm/msm/dp/dp_ctrl.c

196

err = drm_dp_dpcd_writeb(aux, DP_LINK_BW_SET, bw_code);

drivers/gpu/drm/msm/dp/dp_link.c

70

len = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);

drivers/gpu/drm/msm/dp/dp_link.c

781

ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_RESPONSE,

drivers/gpu/drm/msm/dp/dp_link.c

826

ret = drm_dp_dpcd_writeb(link->aux, DP_TEST_EDID_CHECKSUM,

drivers/gpu/drm/msm/dp/dp_link.c

95

err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);

drivers/gpu/drm/nouveau/dispnv50/disp.c

1408

rc = drm_dp_dpcd_writeb(aux, DP_SINK_COUNT_ESI + 1, ack[1]);

drivers/gpu/drm/nouveau/dispnv50/disp.c

1447

ret = drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);

drivers/gpu/drm/nouveau/nouveau_dp.c

313

drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);

drivers/gpu/drm/nouveau/nouveau_dp.c

394

drm_dp_dpcd_writeb(aux, DP_LANE_COUNT_SET, tmp);

drivers/gpu/drm/nouveau/nouveau_dp.c

427

drm_dp_dpcd_writeb(aux, DP_SET_POWER, pwr);

drivers/gpu/drm/radeon/atombios_dp.c

525

drm_dp_dpcd_writeb(&radeon_connector->ddc_bus->aux,

drivers/gpu/drm/radeon/atombios_dp.c

592

drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);

drivers/gpu/drm/radeon/atombios_dp.c

606

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/radeon/atombios_dp.c

609

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/radeon/atombios_dp.c

613

drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);

drivers/gpu/drm/radeon/atombios_dp.c

619

drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);

drivers/gpu/drm/radeon/atombios_dp.c

623

drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);

drivers/gpu/drm/radeon/atombios_dp.c

634

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/radeon/atombios_dp.c

646

drm_dp_dpcd_writeb(dp_info->aux,

drivers/gpu/drm/tegra/dp.c

295

err = drm_dp_dpcd_writeb(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, value);

drivers/gpu/drm/tegra/dp.c

300

err = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET,

drivers/gpu/drm/tegra/dp.c

451

err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, pattern);

drivers/gpu/drm/xlnx/zynqmp_dp.c

1608

ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER,

drivers/gpu/drm/xlnx/zynqmp_dp.c

1637

drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D3);

drivers/gpu/drm/xlnx/zynqmp_dp.c

1858

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET, dpcd_train);

drivers/gpu/drm/xlnx/zynqmp_dp.c

770

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/xlnx/zynqmp_dp.c

840

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/xlnx/zynqmp_dp.c

893

drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL,

drivers/gpu/drm/xlnx/zynqmp_dp.c

897

drm_dp_dpcd_writeb(&dp->aux, DP_DOWNSPREAD_CTRL, 0);

drivers/gpu/drm/xlnx/zynqmp_dp.c

900

ret = drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET, aux_lane_cnt);

drivers/gpu/drm/xlnx/zynqmp_dp.c

906

ret = drm_dp_dpcd_writeb(&dp->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,

drivers/gpu/drm/xlnx/zynqmp_dp.c

913

ret = drm_dp_dpcd_writeb(&dp->aux, DP_LINK_BW_SET, bw_code);

drivers/gpu/drm/xlnx/zynqmp_dp.c

964

ret = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,