drivers/gpu/drm/display/drm_dp_cec.c

100

err = drm_dp_dpcd_write_byte(aux, DP_CEC_TUNNELING_CONTROL, val);

drivers/gpu/drm/display/drm_dp_cec.c

132

return drm_dp_dpcd_write_byte(aux, DP_CEC_TX_MESSAGE_INFO,

drivers/gpu/drm/display/drm_dp_cec.c

153

err = drm_dp_dpcd_write_byte(aux, DP_CEC_TUNNELING_CONTROL, val);

drivers/gpu/drm/display/drm_dp_cec.c

233

drm_dp_dpcd_write_byte(aux, DP_CEC_TUNNELING_IRQ_FLAGS, flags);

drivers/gpu/drm/display/drm_dp_cec.c

262

drm_dp_dpcd_write_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1, DP_CEC_IRQ);

drivers/gpu/drm/display/drm_dp_helper.c

1152

if (drm_dp_dpcd_write_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,

drivers/gpu/drm/display/drm_dp_helper.c

1160

if (drm_dp_dpcd_write_byte(aux, DP_TEST_EDID_CHECKSUM,

drivers/gpu/drm/display/drm_dp_helper.c

1168

if (drm_dp_dpcd_write_byte(aux, DP_TEST_RESPONSE, test_resp) < 0) {

drivers/gpu/drm/display/drm_dp_helper.c

2487

ret = drm_dp_dpcd_write_byte(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);

drivers/gpu/drm/display/drm_dp_helper.c

2514

ret = drm_dp_dpcd_write_byte(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);

drivers/gpu/drm/display/drm_dp_helper.c

3319

err = drm_dp_dpcd_write_byte(aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/display/drm_dp_helper.c

3325

err = drm_dp_dpcd_write_byte(aux,

drivers/gpu/drm/display/drm_dp_helper.c

3741

return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/display/drm_dp_helper.c

3820

return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/display/drm_dp_helper.c

3846

return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);

drivers/gpu/drm/display/drm_dp_helper.c

3862

return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);

drivers/gpu/drm/display/drm_dp_helper.c

3886

return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);

drivers/gpu/drm/display/drm_dp_helper.c

4101

return drm_dp_dpcd_write_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);

drivers/gpu/drm/display/drm_dp_helper.c

4185

return drm_dp_dpcd_write_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);

drivers/gpu/drm/display/drm_dp_helper.c

4261

ret = drm_dp_dpcd_write_byte(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);

drivers/gpu/drm/display/drm_dp_helper.c

4304

ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);

drivers/gpu/drm/display/drm_dp_helper.c

4311

ret = drm_dp_dpcd_write_byte(aux, DP_EDP_BACKLIGHT_FREQ_SET,

drivers/gpu/drm/display/drm_dp_helper.c

4321

ret = drm_dp_dpcd_write_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf);

drivers/gpu/drm/display/drm_dp_helper.c

4468

ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);

drivers/gpu/drm/display/drm_dp_helper.c

961

drm_dp_dpcd_write_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,

drivers/gpu/drm/display/drm_dp_mst_topology.c

3680

ret = drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL,

drivers/gpu/drm/display/drm_dp_mst_topology.c

3698

drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL, 0);

drivers/gpu/drm/display/drm_dp_mst_topology.c

3766

drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL,

drivers/gpu/drm/display/drm_dp_mst_topology.c

3816

ret = drm_dp_dpcd_write_byte(mgr->aux, DP_MSTM_CTRL,

drivers/gpu/drm/display/drm_dp_tunnel.c

1060

if (drm_dp_dpcd_write_byte(aux, DP_TUNNELING_STATUS, bw_req_mask) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

1116

if (drm_dp_dpcd_write_byte(tunnel->aux, DP_REQUEST_BW, request_bw) < 0) {

drivers/gpu/drm/display/drm_dp_tunnel.c

1223

if (drm_dp_dpcd_write_byte(tunnel->aux, DP_TUNNELING_STATUS, val) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

928

if (drm_dp_dpcd_write_byte(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL, val) < 0)

drivers/gpu/drm/i915/display/intel_dp.c

5186

if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, esi[1]) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

5193

if (drm_dp_dpcd_write_byte(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, esi[3]) != 0)