drivers/gpu/drm/amd/amdgpu/atombios_dp.c

386

if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

398

if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

743

if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

529

ret = drm_dp_dpcd_readb(&port->aux, DP_DP13_DPCD_REV, &dpcd_rev);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

536

ret = drm_dp_dpcd_readb(&port->aux, DP_DPCD_REV, &dpcd_rev);

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

108

err = drm_dp_dpcd_readb(&anx6345->aux, DP_MAX_LINK_RATE, &dp_bw);

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

411

err = drm_dp_dpcd_readb(&anx6345->aux, DP_SINK_COUNT, &value);

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

620

err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

783

err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

105

ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

121

ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

168

ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

189

ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

463

drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

476

drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

682

ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

691

ret = drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

742

ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_DOWNSPREAD, &spread);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

796

ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

832

ret = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &sink);

drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

895

val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1360

drm_dp_dpcd_readb(&mhdp->aux, DP_TRAINING_AUX_RD_INTERVAL,

drivers/gpu/drm/bridge/ite-it6505.c

631

ret = drm_dp_dpcd_readb(&it6505->aux, offset, &value);

drivers/gpu/drm/bridge/tc358767.c

1178

ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);

drivers/gpu/drm/bridge/tc358767.c

866

ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, &reg);

drivers/gpu/drm/bridge/tc358767.c

871

ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, &reg);

drivers/gpu/drm/bridge/tc358767.c

877

ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, &reg);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

1022

ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

903

ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

949

ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);

drivers/gpu/drm/display/drm_dp_helper.c

498

ret = drm_dp_dpcd_readb(aux, DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST, &val);

drivers/gpu/drm/display/drm_dp_helper.c

513

ret = drm_dp_dpcd_readb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, &val);

drivers/gpu/drm/display/drm_dp_helper.c

876

err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);

drivers/gpu/drm/display/drm_dp_helper.c

914

err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);

drivers/gpu/drm/i915/display/intel_alpm.c

632

r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val);

drivers/gpu/drm/i915/display/intel_dp.c

236

drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp.c

3834

err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, &val);

drivers/gpu/drm/i915/display/intel_dp.c

4573

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,

drivers/gpu/drm/i915/display/intel_dp.c

4651

if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,

drivers/gpu/drm/i915/display/intel_dp.c

4767

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {

drivers/gpu/drm/i915/display/intel_dp.c

5137

return drm_dp_dpcd_readb(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,

drivers/gpu/drm/i915/display/intel_dp.c

5808

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

182

if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

316

ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1241

ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);

drivers/gpu/drm/i915/display/intel_dp_mst.c

2182

ret = drm_dp_dpcd_readb(intel_dp->mst.mgr.aux, DP_MSTM_CTRL, &val);

drivers/gpu/drm/i915/display/intel_dp_test.c

122

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,

drivers/gpu/drm/i915/display/intel_dp_test.c

145

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,

drivers/gpu/drm/i915/display/intel_dp_test.c

360

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);

drivers/gpu/drm/i915/display/intel_dp_test.c

85

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,

drivers/gpu/drm/i915/display/intel_dp_test.c

94

status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,

drivers/gpu/drm/i915/display/intel_lspcon.c

249

if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV,

drivers/gpu/drm/i915/display/intel_psr.c

3846

ret = drm_dp_dpcd_readb(aux, offset, status);

drivers/gpu/drm/i915/display/intel_psr.c

3853

ret = drm_dp_dpcd_readb(aux, offset, error_status);

drivers/gpu/drm/i915/display/intel_psr.c

3882

r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val);

drivers/gpu/drm/i915/display/intel_psr.c

491

if (drm_dp_dpcd_readb(&intel_dp->aux,

drivers/gpu/drm/mediatek/mtk_dp.c

1767

ret = drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val);

drivers/gpu/drm/mediatek/mtk_dp.c

1775

ret = drm_dp_dpcd_readb(&mtk_dp->aux,

drivers/gpu/drm/msm/dp/dp_link.c

109

if (drm_dp_dpcd_readb(link->aux, addr, &data) < 0) {

drivers/gpu/drm/msm/dp/dp_link.c

200

rlen = drm_dp_dpcd_readb(link->aux,

drivers/gpu/drm/msm/dp/dp_link.c

230

rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_AUDIO_MODE, &data);

drivers/gpu/drm/msm/dp/dp_link.c

387

rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_PATTERN, &bp);

drivers/gpu/drm/msm/dp/dp_link.c

403

rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_MISC0, &bp);

drivers/gpu/drm/msm/dp/dp_link.c

543

rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_LINK_RATE, &bp);

drivers/gpu/drm/msm/dp/dp_link.c

558

rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_LANE_COUNT, &bp);

drivers/gpu/drm/msm/dp/dp_link.c

588

rlen = drm_dp_dpcd_readb(link->aux, DP_PHY_TEST_PATTERN,

drivers/gpu/drm/msm/dp/dp_link.c

61

len = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);

drivers/gpu/drm/msm/dp/dp_link.c

646

rlen = drm_dp_dpcd_readb(link->aux,

drivers/gpu/drm/msm/dp/dp_link.c

664

rlen = drm_dp_dpcd_readb(link->aux, DP_TEST_REQUEST, &data);

drivers/gpu/drm/msm/dp/dp_link.c

88

err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);

drivers/gpu/drm/nouveau/nouveau_dp.c

309

ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);

drivers/gpu/drm/nouveau/nouveau_dp.c

392

if (drm_dp_dpcd_readb(aux, DP_LANE_COUNT_SET, &tmp) == 1) {

drivers/gpu/drm/nouveau/nouveau_dp.c

423

if (drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr) == 1) {

drivers/gpu/drm/radeon/atombios_dp.c

423

if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

drivers/gpu/drm/radeon/atombios_dp.c

435

if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux,

drivers/gpu/drm/radeon/atombios_dp.c

826

if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)

drivers/gpu/drm/tegra/dp.c

196

err = drm_dp_dpcd_readb(aux, DP_EDP_DPCD_REV, &value);

include/drm/display/drm_dp_helper.h

613

ret = drm_dp_dpcd_readb(aux, offset + i, &buf[i]);