drivers/gpu/drm/display/drm_dp_cec.c

147

err = drm_dp_dpcd_read_byte(aux, DP_CEC_TUNNELING_CONTROL, &val);

drivers/gpu/drm/display/drm_dp_cec.c

197

err = drm_dp_dpcd_read_byte(aux, DP_CEC_RX_MESSAGE_INFO, &rx_msg_info);

drivers/gpu/drm/display/drm_dp_cec.c

218

if (drm_dp_dpcd_read_byte(aux, DP_CEC_TUNNELING_IRQ_FLAGS, &flags) < 0)

drivers/gpu/drm/display/drm_dp_cec.c

256

ret = drm_dp_dpcd_read_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1,

drivers/gpu/drm/display/drm_dp_cec.c

272

if (drm_dp_dpcd_read_byte(aux, DP_CEC_TUNNELING_CAPABILITY, &cap) < 0 ||

drivers/gpu/drm/display/drm_dp_helper.c

1131

if (drm_dp_dpcd_read_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,

drivers/gpu/drm/display/drm_dp_helper.c

1139

if (drm_dp_dpcd_read_byte(aux, DP_TEST_REQUEST, &link_edid_read) < 0) {

drivers/gpu/drm/display/drm_dp_helper.c

1866

ret = drm_dp_dpcd_read_byte(aux, DP_SINK_COUNT, &count);

drivers/gpu/drm/display/drm_dp_helper.c

2264

ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

2270

ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK_MISC, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

2483

ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

2510

ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

3264

err = drm_dp_dpcd_read_byte(aux, DP_TEST_LINK_RATE, &rate);

drivers/gpu/drm/display/drm_dp_helper.c

3269

err = drm_dp_dpcd_read_byte(aux, DP_TEST_LANE_COUNT, &lanes);

drivers/gpu/drm/display/drm_dp_helper.c

3277

err = drm_dp_dpcd_read_byte(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);

drivers/gpu/drm/display/drm_dp_helper.c

340

if (drm_dp_dpcd_read_byte(aux, offset, &rd_interval) < 0) {

drivers/gpu/drm/display/drm_dp_helper.c

3567

if (drm_dp_dpcd_read_byte(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,

drivers/gpu/drm/display/drm_dp_helper.c

3592

if (drm_dp_dpcd_read_byte(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &rx_feature) < 0) {

drivers/gpu/drm/display/drm_dp_helper.c

371

if (drm_dp_dpcd_read_byte(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) < 0) {

drivers/gpu/drm/display/drm_dp_helper.c

3756

ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

3785

ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

3877

ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

3901

ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

3926

ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

3955

if (drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)

drivers/gpu/drm/display/drm_dp_helper.c

4090

ret = drm_dp_dpcd_read_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

4176

ret = drm_dp_dpcd_read_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

4250

ret = drm_dp_dpcd_read_byte(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);

drivers/gpu/drm/display/drm_dp_helper.c

4377

ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, &bit_count);

drivers/gpu/drm/display/drm_dp_helper.c

4386

ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);

drivers/gpu/drm/display/drm_dp_helper.c

4394

ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);

drivers/gpu/drm/display/drm_dp_helper.c

4498

ret = drm_dp_dpcd_read_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);

drivers/gpu/drm/display/drm_dp_helper.c

934

ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);

drivers/gpu/drm/display/drm_dp_helper.c

975

ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status);

drivers/gpu/drm/display/drm_dp_mst_topology.c

3625

if (drm_dp_dpcd_read_byte(aux, DP_MSTM_CAP, &mstm_cap) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

1073

if (drm_dp_dpcd_read_byte(aux, DP_TUNNELING_STATUS, &val) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

1217

if (drm_dp_dpcd_read_byte(tunnel->aux, DP_TUNNELING_STATUS, &val) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

1236

if (drm_dp_dpcd_read_byte(tunnel->aux, DP_ESTIMATED_BW, &val) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

1321

if (drm_dp_dpcd_read_byte(aux, DP_TUNNELING_STATUS, &val) < 0)

drivers/gpu/drm/display/drm_dp_tunnel.c

920

if (drm_dp_dpcd_read_byte(tunnel->aux, DP_DPTX_BW_ALLOCATION_MODE_CONTROL, &val) < 0)

drivers/gpu/drm/i915/display/intel_ddi.c

2359

ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status),

drivers/gpu/drm/i915/display/intel_dp.c

4918

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,

drivers/gpu/drm/i915/display/intel_dp.c

5173

if (drm_dp_dpcd_read_byte(&intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &esi[3]) != 0)

drivers/gpu/drm/i915/display/intel_dp.c

6491

if (drm_dp_dpcd_read_byte(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

621

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &bit_min);

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

629

ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &bit_max);

drivers/gpu/drm/i915/display/intel_psr.c

725

ret = drm_dp_dpcd_read_byte(&intel_dp->aux,

drivers/gpu/drm/msm/dp/dp_panel.c

119

rc = drm_dp_dpcd_read_byte(panel->aux, DP_EDP_DPCD_REV, &edp_rev);

drivers/gpu/drm/msm/dp/dp_panel.c

136

rc = drm_dp_dpcd_read_byte(panel->aux, DP_LINK_BW_SET, &bw_set);