drivers/gpu/drm/amd/amdgpu/atombios_dp.c

511

drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3081

ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

653

return drm_dp_dpcd_write(&aconnector->dm_dp_aux.aux,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

724

ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_DATA, rc_data, sizeof(rc_data));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

734

ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_OFFSET, rc_offset, sizeof(rc_offset));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

741

ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_LENGTH, rc_length, sizeof(rc_length));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

747

ret = drm_dp_dpcd_write(aux, SYNAPTICS_RC_COMMAND, &rc_cmd, sizeof(rc_cmd));

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

866

ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

875

ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

914

ret = drm_dp_dpcd_write(port->passthrough_aux,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

922

ret = drm_dp_dpcd_write(aconnector->dsc_aux,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

930

ret = drm_dp_dpcd_write(aconnector->dsc_aux,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

939

ret = drm_dp_dpcd_write(port->passthrough_aux,

drivers/gpu/drm/bridge/analogix/analogix-anx6345.c

200

err = drm_dp_dpcd_write(&anx6345->aux, DP_LINK_BW_SET, dpcd,

drivers/gpu/drm/bridge/analogix/analogix-anx78xx.c

708

err = drm_dp_dpcd_write(&anx78xx->aux, DP_LINK_BW_SET, dpcd,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

260

retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

287

retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

382

retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

444

retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1404

drm_dp_dpcd_write(&mhdp->aux, DP_DOWNSPREAD_CTRL, amp, 2);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

568

err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));

drivers/gpu/drm/bridge/ite-it6505.c

1808

err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));

drivers/gpu/drm/bridge/synopsys/dw-dp.c

583

ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf, lanes);

drivers/gpu/drm/bridge/synopsys/dw-dp.c

644

ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));

drivers/gpu/drm/bridge/synopsys/dw-dp.c

651

ret = drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));

drivers/gpu/drm/bridge/tc358767.c

1197

ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2);

drivers/gpu/drm/bridge/tc358767.c

1205

ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);

drivers/gpu/drm/bridge/tc358767.c

1214

ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);

drivers/gpu/drm/display/drm_dp_aux_dev.c

214

res = drm_dp_dpcd_write(aux_dev->aux, pos, buf, todo);

drivers/gpu/drm/display/drm_dp_helper.c

800

EXPORT_SYMBOL(drm_dp_dpcd_write);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

129

ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->link.cap.lanes);

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

239

ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

293

ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

45

ret = drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf));

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

54

ret = drm_dp_dpcd_write(dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf));

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

99

ret = drm_dp_dpcd_write(dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(buf));

drivers/gpu/drm/i915/display/intel_dp.c

4026

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {

drivers/gpu/drm/i915/display/intel_dp.c

5142

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

222

if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

261

ret = drm_dp_dpcd_write(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

395

ret = drm_dp_dpcd_write(&intel_dp->aux,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

477

ret = drm_dp_dpcd_write(aux,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

66

dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,

drivers/gpu/drm/i915/display/intel_dp_hdcp.c

82

dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1231

return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

549

return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;

drivers/gpu/drm/i915/display/intel_dp_link_training.c

656

ret = drm_dp_dpcd_write(&intel_dp->aux, reg,

drivers/gpu/drm/i915/display/intel_dp_link_training.c

725

drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

drivers/gpu/drm/i915/display/intel_dp_link_training.c

773

drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,

drivers/gpu/drm/i915/display/intel_dp_test.c

328

drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/i915/display/intel_lspcon.c

374

ret = drm_dp_dpcd_write(aux, reg, data, 8);

drivers/gpu/drm/i915/display/intel_lspcon.c

389

ret = drm_dp_dpcd_write(aux, reg, &avi_if_ctrl, 1);

drivers/gpu/drm/i915/display/intel_lspcon.c

448

ret = drm_dp_dpcd_write(aux, reg, (void *)data, 1);

drivers/gpu/drm/i915/display/intel_lspcon.c

474

ret = drm_dp_dpcd_write(aux, reg, &val, 1);

drivers/gpu/drm/i915/display/intel_psr.c

815

drm_dp_dpcd_write(&intel_dp->aux, PANEL_REPLAY_CONFIG,

drivers/gpu/drm/msm/dp/dp_ctrl.c

1367

ret = drm_dp_dpcd_write(ctrl->aux, reg, buf, lane_cnt);

drivers/gpu/drm/msm/dp/dp_ctrl.c

1643

drm_dp_dpcd_write(ctrl->aux, DP_DOWNSPREAD_CTRL, encoding, 2);

drivers/gpu/drm/msm/dp/dp_ctrl.c

1647

drm_dp_dpcd_write(ctrl->aux, DP_EDP_CONFIGURATION_SET,

drivers/gpu/drm/msm/dp/dp_ctrl.c

1867

drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &cfg, 1);

drivers/gpu/drm/radeon/atombios_dp.c

556

drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,

drivers/gpu/drm/tegra/dp.c

286

err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));

drivers/gpu/drm/tegra/dp.c

424

err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, lanes);

drivers/gpu/drm/tegra/dp.c

437

err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_1_SET2, values,

drivers/gpu/drm/xlnx/zynqmp_dp.c

1852

ret = drm_dp_dpcd_write(&dp->aux, DP_LINK_QUAL_LANE0_SET,

drivers/gpu/drm/xlnx/zynqmp_dp.c

729

ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set,

include/drm/display/drm_dp_helper.h

556

ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,

include/drm/display/drm_dp_helper.h

641

ret = drm_dp_dpcd_write(aux, offset, buffer, size);

include/drm/display/drm_dp_helper.h

663

return drm_dp_dpcd_write(aux, offset, &value, 1);