drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2708

struct dwbc *dwb = params->dwbc_enable_params.dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2717

struct dwbc *dwb = params->dwbc_disable_params.dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2725

struct dwbc *dwb = params->dwbc_update_params.dwb;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3386

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3470

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3482

struct dwbc *dwb)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

545

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

566

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

587

struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

599

struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

617

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

697

struct dwbc *dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

45

static bool dwb1_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

64

static bool dwb1_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

66

struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

69

dwbc->funcs->disable(dwbc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

81

static bool dwb1_disable(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c

83

struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h

254

struct dwbc base;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

101

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

121

dwb2_config_dwb_cnv(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

124

dwb2_set_scaler(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

135

bool dwb2_disable(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

137

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

158

static bool dwb2_update(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

160

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

185

dwb2_config_dwb_cnv(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

188

dwb2_set_scaler(dwbc, params);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

198

bool dwb2_is_enabled(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

200

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

210

void dwb2_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

213

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

226

void dwb2_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

229

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

235

static void dwb2_set_warmup(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

238

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

250

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

252

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

50

static bool dwb2_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

52

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

72

void dwb2_config_dwb_cnv(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

74

struct dcn20_dwbc *dwbc20 = TO_DCN20_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c

99

static bool dwb2_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

389

struct dwbc base;

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

402

bool dwb2_disable(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

404

bool dwb2_is_enabled(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

406

void dwb2_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

409

void dwb2_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

412

void dwb2_config_dwb_cnv(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h

415

void dwb2_set_scaler(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

100

dwb3_config_fc(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

103

dwb3_program_hdr_mult(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

104

dwb3_set_gamut_remap(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

105

dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

108

dwb3_set_denorm(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

119

bool dwb3_disable(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

121

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

129

DC_LOG_DWB("%s dwb3_disabled at inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

133

void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

135

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

151

DC_LOG_DWB("%s dwb3_fc_disabled at inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

155

bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

157

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

167

DC_LOG_DWB("%s dwb update, inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

175

dwb3_config_fc(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

178

dwb3_program_hdr_mult(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

179

dwb3_set_gamut_remap(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

180

dwb3_ogam_set_input_transfer_func(dwbc, params->out_transfer_func);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

183

dwb3_set_denorm(dwbc, params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

193

bool dwb3_is_enabled(struct dwbc *dwbc)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

195

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

205

void dwb3_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

208

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

220

void dwb3_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

223

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

228

void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

230

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

46

static bool dwb3_get_caps(struct dwbc *dwbc, struct dwb_caps *caps)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

66

void dwb3_config_fc(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

68

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

88

dwb3_set_stereo(dwbc, &params->stereo_params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

91

bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params)

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

93

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.c

94

DC_LOG_DWB("%s dwb3_enabled at inst = %d", __func__, dwbc->inst);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

871

struct dwbc base;

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

884

bool dwb3_enable(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

886

bool dwb3_disable(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

888

bool dwb3_update(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

890

bool dwb3_is_enabled(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

892

void dwb3_set_fc_enable(struct dwbc *dwbc, enum dwb_frame_capture_enable enable);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

894

void dwb3_set_stereo(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

897

void dwb3_set_new_content(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

900

void dwb3_config_fc(struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

903

void dwb3_set_denorm(struct dwbc *dwbc, struct dc_dwb_params *params);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

906

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

910

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb.h

914

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

273

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

276

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

286

cm_helper_translate_curve_to_hw_format(dwbc->ctx,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

301

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

306

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

356

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

359

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

365

dwb3_program_gamut_remap(dwbc, NULL, adjust.gamut_coef_format, CM_GAMUT_REMAP_MODE_BYPASS);

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

379

dwb3_program_gamut_remap(dwbc, arr_reg_val,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

382

dwb3_program_gamut_remap(dwbc, arr_reg_val,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

389

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/dwb/dcn30/dcn30_dwb_cm.c

392

struct dcn30_dwbc *dwbc30 = TO_DCN30_DWBC(dwbc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2530

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2536

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2556

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

2560

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3212

res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

334

res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

458

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

459

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

475

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

481

dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

532

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

535

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

558

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

562

dwb = dc->res_pool->dwbc[dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

581

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

626

dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3208

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3243

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3266

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3272

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3299

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3305

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3324

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3330

dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1771

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1799

struct dwbc *dwb,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

1803

struct dwbc *dwb);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

506

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

511

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

515

struct dwbc *dwb;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

262

struct dwbc *dwbc[MAX_DWB_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

496

struct dwbc *dwbc;

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

177

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

181

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

184

bool (*disable)(struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

187

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

191

struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

194

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

198

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

202

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

206

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

211

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

215

struct dwbc *dwbc, unsigned int *buf_idx,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

220

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

225

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

230

struct dwbc *dwbc,

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

234

struct dwbc *dwbc, uint32_t *time_stamp);

drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h

237

struct dwbc *dwbc);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1184

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1185

kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1186

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2289

pool->dwbc[i] = &dwbc20->base;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

748

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

749

kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

750

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1175

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1176

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1177

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1269

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1146

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1147

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1148

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1229

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1099

if (pool->dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1100

kfree(TO_DCN30_DWBC(pool->dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1101

pool->dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

754

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1043

if (pool->dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1044

kfree(TO_DCN30_DWBC(pool->dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1045

pool->dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

715

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1474

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1475

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1476

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

1565

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1532

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1533

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1534

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1623

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1475

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1476

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1477

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

1566

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1470

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1471

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1472

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1558

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1478

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1479

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1480

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1563

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1458

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1459

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1460

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1543

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1542

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1543

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1544

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

1658

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1522

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1523

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1524

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

1638

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1529

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1530

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1531

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

1645

pool->dwbc[i] = &dwbc30->base;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1484

if (pool->base.dwbc[i] != NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1485

kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1486

pool->base.dwbc[i] = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1570

pool->dwbc[i] = &dwbc401->base;