Symbol: drm_dp_channel_eq_ok
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
464
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
drivers/gpu/drm/amd/amdgpu/atombios_dp.c
689
if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
411
if (drm_dp_channel_eq_ok(link_status, lane_count)) {
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
596
if (!drm_dp_channel_eq_ok(link_status, dp->link_train.lane_count)) {
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
1017
if (drm_dp_channel_eq_ok(link_status, mhdp->link.num_lanes)) {
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
2126
drm_dp_channel_eq_ok(status, mhdp->link.num_lanes) &&
drivers/gpu/drm/bridge/ite-it6505.c
1971
if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
drivers/gpu/drm/bridge/ite-it6505.c
2261
if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
drivers/gpu/drm/bridge/ite-it6505.c
2489
if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
drivers/gpu/drm/bridge/synopsys/dw-dp.c
1004
if (!drm_dp_channel_eq_ok(status, link->lanes)) {
drivers/gpu/drm/bridge/synopsys/dw-dp.c
1611
return !drm_dp_channel_eq_ok(link_status, dp->link.lanes);
drivers/gpu/drm/bridge/synopsys/dw-dp.c
859
if (drm_dp_channel_eq_ok(status, link->lanes)) {
drivers/gpu/drm/display/drm_dp_helper.c
110
EXPORT_SYMBOL(drm_dp_channel_eq_ok);
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
281
if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) {
drivers/gpu/drm/i915/display/intel_dp.c
5691
ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1097
if (drm_dp_channel_eq_ok(link_status,
drivers/gpu/drm/i915/display/intel_dp_link_training.c
1153
if (!drm_dp_channel_eq_ok(link_status,
drivers/gpu/drm/mediatek/mtk_dp.c
1719
if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {
drivers/gpu/drm/msm/dp/dp_ctrl.c
1584
if (drm_dp_channel_eq_ok(link_status,
drivers/gpu/drm/msm/dp/dp_ctrl.c
2265
return drm_dp_channel_eq_ok(link_status, num_lanes);
drivers/gpu/drm/msm/dp/dp_link.c
959
bool channel_eq_done = drm_dp_channel_eq_ok(link->link_status,
drivers/gpu/drm/nouveau/nouveau_dp.c
352
if (!drm_dp_channel_eq_ok(stat, outp->dp.lt.nr)) {
drivers/gpu/drm/nouveau/nouveau_dp.c
460
if (drm_dp_channel_eq_ok(link_status, outp->dp.lt.nr))
drivers/gpu/drm/radeon/atombios_dp.c
507
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
drivers/gpu/drm/radeon/atombios_dp.c
749
if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
drivers/gpu/drm/rockchip/cdn-dp-core.c
545
return drm_dp_channel_eq_ok(link_status, min(port->lanes, sink_lanes));
drivers/gpu/drm/tegra/dp.c
603
if (!drm_dp_channel_eq_ok(status, link->lanes))
drivers/gpu/drm/tegra/dp.c
770
if (!drm_dp_channel_eq_ok(status, link->lanes)) {
drivers/gpu/drm/xlnx/zynqmp_dp.c
2351
!drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
drivers/gpu/drm/xlnx/zynqmp_dp.c
855
ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
include/drm/display/drm_dp_helper.h
36
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],