drm_crtc_accurate_vblank_count
drm_crtc_accurate_vblank_count(&acrtc_attach->base);
drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
drm_crtc_accurate_vblank_count(crtc), crcs);
e->sequence = drm_crtc_accurate_vblank_count(crtc) + 1;
EXPORT_SYMBOL(drm_crtc_accurate_vblank_count);
drm_crtc_accurate_vblank_count(&crtc->base) + 1,
drm_crtc_accurate_vblank_count(&crtc->base) + 1,
return (u32)drm_crtc_accurate_vblank_count(&crtc->base);
drm_crtc_accurate_vblank_count(&crtc->base) + 1,
drm_crtc_accurate_vblank_count(&crtc->base),
drm_crtc_accurate_vblank_count(&crtc->base);
drm_crtc_accurate_vblank_count(&crtc->base);
drm_crtc_accurate_vblank_count(crtc), crcs);
drm_crtc_accurate_vblank_count(crtc), crcs);
vbc = drm_crtc_accurate_vblank_count(&mxsfb->crtc);
drm_crtc_accurate_vblank_count(crtc);
drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc);
u64 frame = drm_crtc_accurate_vblank_count(crtc);
u64 frame = drm_crtc_accurate_vblank_count(crtc);
u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc);