dw32
dw32(SIAStatus, NonselPortActive | SelPortActive);
dw32 (BusMode, CmdReset);
dw32 (BusMode, de_bus_mode);
dw32(CSR13, 0); /* Reset phy */
dw32(RxRingAddr, de->ring_dma);
dw32(TxRingAddr, de->ring_dma + (sizeof(struct de_desc) * DE_RX_RING_SIZE));
dw32(MacMode, RxTx | macmode);
dw32(IntrMask, de_intr_mask);
dw32(IntrMask, 0);
dw32(SIAStatus, (status & ~NWayState) | NWayRestart);
dw32 (ROMCmd, 0); /* Reset the pointer with a dummy write. */
dw32(MacStatus, status);
dw32(RxPoll, NormalRxPoll);
dw32(TxPoll, NormalTxPoll);
dw32(TxPoll, NormalTxPoll);
dw32(MacMode, macmode);
dw32(MacMode, macmode & ~RxTx);
dw32(MacMode, macmode | RxTx);
dw32(IntrMask, 0);
dw32(MacStatus, dr32(MacStatus));
dw32(CSR11, FULL_DUPLEX_MAGIC);
dw32(CSR13, 0); /* Reset phy */
dw32(CSR14, de->media[media].csr14);
dw32(CSR15, de->media[media].csr15);
dw32(CSR13, de->media[media].csr13);
dw32(MacMode, macmode);
dw32(DCR1, 0x1); /* Tx polling again */
dw32(DCR7, 0); /* Disable Interrupt */
dw32(DCR5, dr32(DCR5));
dw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
dw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
dw32(DCR6, cr6_tmp);
dw32(DCR6, cr6_data);
dw32(DCR1, 0x1); /* Issue Tx polling */
dw32(DCR9, data | cmd[i]);
dw32(DCR9, CR9_SROM_READ);
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
dw32(DCR9, CR9_SROM_READ | CR9_SRCS);
dw32(DCR9, CR9_SROM_READ);
dw32(DCR9, phy_data); /* MII Clock Low */
dw32(DCR9, phy_data | MDCLKH); /* MII Clock High */
dw32(DCR9, phy_data); /* MII Clock Low */
dw32(DCR9, 0x50000);
dw32(DCR9, 0x40000);
dw32(DCR7, 0);
dw32(DCR5, dr32(DCR5));
dw32(DCR0, DM910X_RESET); /* RESET MAC */
dw32(DCR0, db->cr0_data);
dw32(DCR12, 0x180); /* Let bit 7 output port */
dw32(DCR12, 0x80); /* Issue RESET signal */
dw32(DCR12, 0x0); /* Clear RESET signal */
dw32(DCR7, db->cr7_data);
dw32(DCR15, db->cr15_data);
dw32(DCR7, 0);
dw32(DCR1, 0x1); /* Issue Tx polling */
dw32(DCR1, 0x1); /* Issue Tx polling */
dw32(DCR7, db->cr7_data);
dw32(DCR0, DM910X_RESET);
dw32(DCR5, db->cr5_data);
dw32(DCR7, 0);
dw32(DCR7, db->cr7_data);
dw32(DCR1, 0x1); /* Issue Tx polling */
dw32(HashTable0, hash_table[0]);
dw32(HashTable1, hash_table[1]);
dw32(ASICCtrl, mode);
dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
dw32(RFDListPtr0, np->rx_ring_dma);
dw32(RFDListPtr1, 0);
dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
dw32(RmonStatMask, 0x0007ffff);
dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
dw32(VLANTag, 0x8100 << 16 | np->vlan);
dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
dw32(CountDown, 10000);
dw32(TFDListPtr0, np->tx_ring_dma +
dw32(TFDListPtr1, 0);
dw32(CountDown, 100);
dw32(TFDListPtr0, np->tx_ring_dma +
dw32(TFDListPtr1, 0);
dw32(MACCtrl, dr16(MACCtrl) | TxEnable);