drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1439

static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg *catalog,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

182

struct dpu_hw_intf *hw_intf;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

265

struct dpu_hw_intf *hw_intf;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

519

struct dpu_hw_intf *hw_intf;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

103

static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

276

struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

285

struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

309

struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

327

struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

347

static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

359

static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

364

static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

369

static int dpu_hw_intf_enable_te(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

402

static void dpu_hw_intf_setup_autorefresh_config(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

425

static bool dpu_hw_intf_get_autorefresh_config(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

435

static int dpu_hw_intf_disable_te(struct dpu_hw_intf *intf)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

447

static int dpu_hw_intf_connect_external_te(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

470

static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

497

static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

510

static void dpu_hw_intf_vsync_sel_v8(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

546

static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

590

static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

612

struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

617

struct dpu_hw_intf *c;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

103

int (*enable_tearcheck)(struct dpu_hw_intf *intf, struct dpu_hw_tear_check *cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

105

int (*disable_tearcheck)(struct dpu_hw_intf *intf);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

107

int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

109

void (*vsync_sel)(struct dpu_hw_intf *intf, struct dpu_vsync_source_cfg *cfg);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

111

void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

113

void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

130

struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

14

struct dpu_hw_intf;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

81

void (*setup_timing_gen)(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

85

void (*setup_prg_fetch)(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

88

void (*enable_timing)(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

91

void (*get_status)(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

94

u32 (*get_line_count)(struct dpu_hw_intf *intf);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

96

void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

98

void (*setup_misr)(struct dpu_hw_intf *intf);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h

99

int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

103

struct dpu_hw_intf *hw;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

103

static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

33

struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];