drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

186

struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2352

struct dpu_hw_cwb *hw_cwb;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

18

static void dpu_hw_cwb_config(struct dpu_hw_cwb *ctx,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

55

struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.c

59

struct dpu_hw_cwb *c;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

11

struct dpu_hw_cwb;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

35

void (*config_cwb)(struct dpu_hw_cwb *ctx,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

60

static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

62

return container_of(hw, struct dpu_hw_cwb, base);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

65

struct dpu_hw_cwb *dpu_hw_cwb_init(struct drm_device *dev,

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

129

struct dpu_hw_cwb *hw;