drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1435

struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_CRTC];

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1436

struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_CRTC];

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

1437

struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_CRTC];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1160

struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1161

struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1162

struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1163

struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1235

struct dpu_hw_blk *hw_cdm = NULL;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2183

struct dpu_hw_blk *hw_lm[2];

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

2358

struct dpu_hw_blk *rt_pp_list[MAX_CHANNELS_PER_ENC];

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

114

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h

129

static inline struct dpu_hw_cdm *to_dpu_hw_cdm(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

320

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h

349

static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

47

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cwb.h

60

static inline struct dpu_hw_cwb *to_dpu_hw_cwb(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

58

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

78

static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h

102

static inline struct dpu_hw_dspp *to_dpu_hw_dspp(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dspp.h

86

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

108

static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h

87

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h

26

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.h

42

static inline struct dpu_hw_merge_3d *to_dpu_hw_merge_3d(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h

116

static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw)

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h

99

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

310

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h

149

struct dpu_hw_blk base;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

897

enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size)

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

900

struct dpu_hw_blk **hw_blks;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

982

struct dpu_hw_blk *blk,

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

30

struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

31

struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

32

struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

35

struct dpu_hw_blk *cwb_blks[CWB_MAX - CWB_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

36

struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

37

struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

38

struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

40

struct dpu_hw_blk *cdm_blk;

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h

93

enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);