drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3338

if (dpp && dpp->funcs->dpp_reset)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3339

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

548

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1458

void dpp_reset(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

383

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

267

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1501

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

110

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

99

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

225

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

295

.dpp_reset = dpp_reset,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1550

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1713

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3199

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

293

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

738

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

901

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3078

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

148

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

243

void (*dpp_reset)(struct dpp *dpp);