drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

461

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

462

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

463

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

464

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

465

dpp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

466

dpp_regs(4),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

467

dpp_regs(5),

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

805

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

409

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

410

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

411

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

412

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

413

dpp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

728

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

641

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

642

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

643

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

644

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

645

dpp_regs(3),

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

646

dpp_regs(4)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

664

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

622

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

623

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

624

dpp_regs(1)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

642

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

523

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

524

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

525

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

526

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

527

dpp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

987

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1022

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

529

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

530

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

531

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

532

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

533

dpp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

526

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

527

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

528

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

529

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

530

dpp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

986

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

517

static const struct dcn3_dpp_registers dpp_regs[] = {

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

518

dpp_regs(0),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

519

dpp_regs(1),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

520

dpp_regs(2),

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

521

dpp_regs(3)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

979

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1005

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

1012

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

411

static struct dcn3_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1000

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

404

static struct dcn3_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

993

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

424

static struct dcn3_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

870

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

876

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

404

static struct dcn3_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

850

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

856

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

405

static struct dcn3_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

857

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

863

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

1002

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

385

static struct dcn401_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

995

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1028

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1035

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

359

static struct dcn42_dpp_registers dpp_regs[4];

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1063

#define REG_STRUCT dpp_regs

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1070

&dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

383

static struct dcn42_dpp_registers dpp_regs[4];