drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

10205

adev->dm.dc->caps.color.dpp.gamma_corr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1146

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1747

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c

1917

bool has_3dlut = adev->dm.dc->caps.color.dpp.hw_3d_lut || adev->dm.dc->caps.color.mpc.preblend;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_colorop.c

233

bool hw_3d_lut = adev->dm.dc->caps.color.dpp.hw_3d_lut ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

782

has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1406

adev->dm.dc->caps.color.dpp.gamma_corr)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c

1639

struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

169

pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c

170

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

337

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

338

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

339

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

344

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

307

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

308

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

309

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

314

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

331

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

570

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

571

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

572

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

577

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

180

if (context->res_ctx.pipe_ctx[i].plane_res.dpp)

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

181

dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

182

else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

187

} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c

204

struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc.c

3888

(!tmp_pipe->plane_res.xfm && !tmp_pipe->plane_res.dpp) ||

drivers/gpu/drm/amd/display/dc/core/dc.c

3889

(!tmp_pipe->plane_res.ipp && !tmp_pipe->plane_res.dpp))

drivers/gpu/drm/amd/display/dc/core/dc.c

7462

state->dpp[i].dpp_clock_enable = (pipe_ctx->plane_res.dpp != NULL) ? 1 : 0;

drivers/gpu/drm/amd/display/dc/core/dc.c

7469

state->dpp[i].recout_start_x = dscl_data->recout.x;

drivers/gpu/drm/amd/display/dc/core/dc.c

7470

state->dpp[i].recout_start_y = dscl_data->recout.y;

drivers/gpu/drm/amd/display/dc/core/dc.c

7471

state->dpp[i].recout_width = dscl_data->recout.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7472

state->dpp[i].recout_height = dscl_data->recout.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7475

state->dpp[i].mpc_width = dscl_data->mpc_size.width;

drivers/gpu/drm/amd/display/dc/core/dc.c

7476

state->dpp[i].mpc_height = dscl_data->mpc_size.height;

drivers/gpu/drm/amd/display/dc/core/dc.c

7479

state->dpp[i].dscl_mode = dscl_data->dscl_mode;

drivers/gpu/drm/amd/display/dc/core/dc.c

7482

state->dpp[i].horz_ratio_int = dscl_data->ratios.h_scale_ratio >> 19; // Extract integer part from programmed ratio

drivers/gpu/drm/amd/display/dc/core/dc.c

7483

state->dpp[i].vert_ratio_int = dscl_data->ratios.v_scale_ratio >> 19; // Extract integer part from programmed ratio

drivers/gpu/drm/amd/display/dc/core/dc.c

7486

state->dpp[i].h_taps = dscl_data->taps.h_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back

drivers/gpu/drm/amd/display/dc/core/dc.c

7487

state->dpp[i].v_taps = dscl_data->taps.v_taps + 1; // dscl_prog_data.taps stores (taps - 1), so add 1 back

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1086

block_sequence[*num_steps].params.control_cm_hist_params.dpp

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1087

= current_mpc_pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1096

if (current_mpc_pipe->plane_res.dpp &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1097

current_mpc_pipe->plane_res.dpp->funcs->set_cursor_matrix &&

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1099

block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.dpp = current_mpc_pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2107

struct dpp *dpp, uint32_t hw_mult)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2110

seq_state->steps[*seq_state->num_steps].params.dpp_set_hdr_multiplier_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2325

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2331

if (dpp && dpp->funcs->dpp_setup) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2333

dpp->funcs->dpp_setup(dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2345

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2350

if (dpp->funcs->dpp_program_bias_and_scale)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2351

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2436

struct dpp *dpp = params->control_cm_hist_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2438

if (dpp && dpp->funcs->dpp_cm_hist_control)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2439

dpp->funcs->dpp_cm_hist_control(dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2828

struct dpp *dpp = params->dpp_set_hdr_multiplier_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2831

if (dpp->funcs->dpp_set_hdr_multiplier)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2832

dpp->funcs->dpp_set_hdr_multiplier(dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3241

struct dpp *dpp = params->dpp_dppclk_control_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3245

if (dpp && dpp->funcs->dpp_dppclk_control)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3246

dpp->funcs->dpp_dppclk_control(dpp, dppclk_div, enable);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3336

struct dpp *dpp = params->dpp_reset_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3338

if (dpp && dpp->funcs->dpp_reset)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3339

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3434

struct dpp *dpp = params->dpp_set_cursor_matrix_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3438

if (dpp && dpp->funcs->set_cursor_matrix)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3439

dpp->funcs->set_cursor_matrix(dpp, color_space, *cursor_csc_color_matrix);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3488

struct dpp *dpp = params->dpp_set_scaler_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3491

if (dpp && dpp->funcs->dpp_set_scaler)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3492

dpp->funcs->dpp_set_scaler(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3579

struct dpp *dpp = params->dpp_set_cursor_attributes_params.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3582

if (dpp && dpp->funcs->set_cursor_attributes)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3583

dpp->funcs->set_cursor_attributes(dpp, attributes);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4077

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4083

seq_state->steps[*seq_state->num_steps].params.control_cm_hist_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4311

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4317

seq_state->steps[*seq_state->num_steps].params.dpp_dppclk_control_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4449

struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4453

seq_state->steps[*seq_state->num_steps].params.dpp_reset_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4629

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4635

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_matrix_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4643

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4648

seq_state->steps[*seq_state->num_steps].params.dpp_set_scaler_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4705

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

4710

seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.dpp = dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

886

block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.dpp =

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

887

current_pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

954

(!current_pipe->plane_res.xfm && !current_pipe->plane_res.dpp) ||

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

955

(!current_pipe->plane_res.ipp && !current_pipe->plane_res.dpp))

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1018

if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1022

*dpp_offset *= pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1617

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1618

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1619

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1629

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1630

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1631

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1644

if (pipe_ctx->plane_res.dpp != NULL)

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1645

res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

1646

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2395

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2399

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2411

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2419

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2422

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2429

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2432

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2439

pipe->plane_res.dpp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2441

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2448

pipe->plane_res.dpp->inst);

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2450

pipe->plane_res.dpp->inst,

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

2652

split_pipe->plane_res.dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

3998

pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

4143

pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

5870

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

470

(!pipe_ctx->plane_res.xfm && !pipe_ctx->plane_res.dpp) ||

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

471

(!pipe_ctx->plane_res.ipp && !pipe_ctx->plane_res.dpp))

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

162

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

164

if (dpp && dpp->funcs->dpp_cm_hist_read)

drivers/gpu/drm/amd/display/dc/core/dc_surface.c

165

dpp->funcs->dpp_cm_hist_read(dpp, &pipe_ctx->plane_state->status.cm_hist);

drivers/gpu/drm/amd/display/dc/dc.h

3174

} dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/dc.h

325

struct dpp_color_caps dpp;

drivers/gpu/drm/amd/display/dc/dc.h

867

bool dpp: 1;

drivers/gpu/drm/amd/display/dc/dc.h

887

bool dpp : 1; /* Display pipes and planes */

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1076

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1085

pl->position_cfg.pDpp.cur0_ctl.raw = dpp->pos.cur0_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1091

const struct hubp *hubp, const struct dpp *dpp)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1102

pl_A->aDpp.cur0_ctl.raw = dpp->att.cur0_ctl.raw;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1147

pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1157

pipe_idx, pCtx->plane_res.hubp, pCtx->plane_res.dpp);

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

1315

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && !disallow_rcg)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

372

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable)

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

398

if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && allow_rcg)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

343

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

344

copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

153

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c

154

copy_settings_data->dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

343

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

346

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c

353

dpp->inst, s.igam_input_format,

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

318

if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) {

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

333

input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs->

drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c

541

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

1861

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h

474

} dpp;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13220

out->informative.dpp.total_num_dpps_required = 0;

drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c

13223

out->informative.dpp.total_num_dpps_required += mode_lib->mp.NoOfDPP[k];

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

125

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

131

dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

137

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

138

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

174

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

192

void dpp_reset(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

194

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

196

dpp->filter_h_c = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

197

dpp->filter_v_c = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

198

dpp->filter_h = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

199

dpp->filter_v = NULL;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

204

memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

205

memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

213

struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

215

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

229

re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

230

if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

234

dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

236

if (dpp->is_write_to_ram_a_safe)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

243

dpp->pwl_data = *params;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

245

re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

246

dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

269

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

272

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

284

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

298

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

42

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

421

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

425

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

442

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

448

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

45

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

49

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

503

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

506

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

520

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

524

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

527

if (dpp->tf_mask->DPPCLK_RATE_CONTROL)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

537

void dpp_force_disable_cursor(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

539

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

587

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

594

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

596

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

597

dpp->base.funcs = &dcn10_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

598

dpp->base.caps = &dcn10_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

600

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

601

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

602

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

604

dpp->lb_pixel_depth_supported =

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

610

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

611

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

94

void dpp_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.c

97

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1360

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1385

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1389

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1396

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1411

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1415

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1419

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1423

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1429

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1433

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1439

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1443

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1446

void dpp1_full_bypass(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1449

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1452

void dpp1_set_degamma_pwl(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1455

void dpp_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1458

void dpp_reset(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1461

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1466

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1470

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1475

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1480

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1483

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1487

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1491

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1495

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1499

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1507

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1512

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1516

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1527

void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

1529

void dpp_force_disable_cursor(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

30

#define TO_DCN10_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h

31

container_of(dpp, struct dcn10_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

115

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

116

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

117

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

118

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

126

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

136

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

146

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

158

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

161

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

166

program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

177

program_gamut_remap(dpp, arr_reg_val, GAMUT_REMAP_COEFF);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

181

static void read_gamut_remap(struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

193

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

194

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

195

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

196

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

204

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

214

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

224

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

230

void dpp1_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

233

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

237

read_gamut_remap(dpp, arr_reg_val, &select);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

250

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

278

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

279

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_OCSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

280

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

281

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_OCSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

296

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

305

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

308

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

318

dpp1_cm_program_color_matrix(dpp, regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

322

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

325

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

326

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

327

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

328

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

329

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

330

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

331

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

332

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

334

reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

335

reg->masks.field_region_end = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

336

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

337

reg->masks.field_region_end_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

338

reg->shifts.field_region_end_base = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

339

reg->masks.field_region_end_base = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

340

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

341

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

342

reg->shifts.exp_region_start = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

343

reg->masks.exp_region_start = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

344

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

345

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

349

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

352

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

353

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

354

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

355

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

356

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

357

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

358

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

359

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_DGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

361

reg->shifts.field_region_end = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

362

reg->masks.field_region_end = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

363

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

364

reg->masks.field_region_end_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

365

reg->shifts.field_region_end_base = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

366

reg->masks.field_region_end_base = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

367

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

368

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

369

reg->shifts.exp_region_start = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

370

reg->masks.exp_region_start = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

371

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

372

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_DGAM_RAMB_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

375

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

378

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

380

dpp1_cm_program_color_matrix(dpp, regval);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

383

void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

386

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

393

void dpp1_cm_program_regamma_lut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

398

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

417

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

420

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

43

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

431

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

434

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

437

dpp1_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

454

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

46

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

460

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

463

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

466

dpp1_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

483

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

487

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

492

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

50

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

535

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

536

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

537

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

538

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

553

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

563

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

566

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

584

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

587

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

590

dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

608

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

613

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

616

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

619

dpp1_cm_get_degamma_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

636

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

640

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

643

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

651

struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

653

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

660

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

663

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

687

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

690

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

700

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

705

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

721

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

728

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

750

void dpp1_set_degamma_pwl(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

768

void dpp1_full_bypass(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

770

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

783

if (dpp->tf_mask->CM_BYPASS_EN)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

792

static bool dpp1_ingamma_ram_inuse(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

797

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

824

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

828

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

873

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

876

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_cm.c

89

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

124

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

158

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

161

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

163

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

168

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

169

dpp->base.ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

170

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

180

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

187

if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

207

if (dpp->base.caps->max_lb_partitions == 31)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

241

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

279

struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

321

filter_updated = (filter_h && (filter_h != dpp->filter_h))

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

322

|| (filter_v && (filter_v != dpp->filter_v));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

329

filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

330

|| (filter_v_c && (filter_v_c != dpp->filter_v_c));

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

338

dpp, scl_data->taps.h_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

341

dpp->filter_h = filter_h;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

344

dpp, scl_data->taps.v_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

347

dpp->filter_v = filter_v;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

351

dpp, scl_data->taps.h_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

356

dpp, scl_data->taps.v_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

360

dpp->filter_h_c = filter_h_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

361

dpp->filter_v_c = filter_v_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

364

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

365

dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

44

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

459

static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

468

if (dpp->base.ctx->dc->debug.use_max_lb) {

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

47

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

475

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

482

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

491

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

499

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

51

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

511

struct dcn10_dpp *dpp, const struct scaler_data *data)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

587

static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

613

void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

617

struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

623

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

628

dpp->scl_data = *scl_data;

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

646

dpp1_dscl_set_recout(dpp, &scl_data->recout);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

665

lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

666

dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

685

dpp1_dscl_set_manual_ratio_init(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp_dscl.c

694

dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

101

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

108

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

320

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

323

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

343

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

347

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

372

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

376

(void)dpp;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

414

struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

42

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

421

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

423

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

424

dpp->base.funcs = &dcn20_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

425

dpp->base.caps = &dcn20_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

427

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

428

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

429

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

431

dpp->lb_pixel_depth_supported =

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

437

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

438

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

45

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

49

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

51

void dpp20_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

54

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

78

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

81

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.c

93

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

29

#define TO_DCN20_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

30

container_of(dpp, struct dcn20_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

678

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

709

void dpp20_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

713

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

717

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

721

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

725

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

731

struct dpp *dpp_base, const struct pwl_params *params);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

734

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

738

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

742

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

759

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

763

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

767

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

772

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

783

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h

786

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1014

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1021

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1036

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1040

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1051

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1056

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1085

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1090

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1106

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1109

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1117

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

117

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1197

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

1200

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

135

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

138

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

162

struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

189

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

190

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

191

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

192

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

203

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

214

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

217

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

222

program_gamut_remap(dpp, NULL, DCN2_GAMUT_REMAP_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

233

program_gamut_remap(dpp, arr_reg_val, DCN2_GAMUT_REMAP_COEF_A);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

237

static void read_gamut_remap(struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

250

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

251

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

252

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

253

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

259

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

267

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

273

void dpp2_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

276

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

280

read_gamut_remap(dpp, arr_reg_val, &select);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

293

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

298

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

339

icsc_regs.shifts.csc_c11 = dpp->tf_shift->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

340

icsc_regs.masks.csc_c11 = dpp->tf_mask->CM_ICSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

341

icsc_regs.shifts.csc_c12 = dpp->tf_shift->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

342

icsc_regs.masks.csc_c12 = dpp->tf_mask->CM_ICSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

357

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

366

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

369

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

37

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

377

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

380

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

390

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

395

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

414

struct dcn20_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

417

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

418

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

419

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

420

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

421

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

422

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

423

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

424

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

426

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

427

reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

428

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

429

reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

43

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

430

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

431

reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

432

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

433

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

434

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

435

reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

436

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

437

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

442

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

445

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

448

dcn20_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

465

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

47

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

470

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

473

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

476

dcn20_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

493

cm_helper_program_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

496

static enum dc_lut_mode dpp20_get_blndgam_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

500

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

51

struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

523

struct dpp *dpp_base, const struct pwl_params *params)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

527

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

53

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

558

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

566

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

589

static enum dc_lut_mode dpp20_get_shaper_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

593

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

616

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

619

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

631

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

635

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

65

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

70

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

781

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

785

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

86

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

93

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

932

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

938

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

968

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp_cm.c

974

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

191

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

198

dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

203

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

204

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

251

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

298

struct dcn201_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

305

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

307

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

308

dpp->base.funcs = &dcn201_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

309

dpp->base.caps = &dcn201_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

311

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

312

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

313

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

315

dpp->lb_pixel_depth_supported =

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

320

dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

321

dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

35

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

38

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

42

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

45

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.c

52

struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

30

#define TO_DCN201_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

31

container_of(dpp, struct dcn201_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn201/dcn201_dpp.h

58

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

105

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1075

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1079

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

110

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1225

static bool dpp3_program_shaper(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1231

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1266

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1272

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1313

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1320

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1335

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1339

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1350

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1355

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1384

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1389

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1405

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1408

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1415

static bool dpp3_program_3dlut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

150

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_POST_CSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

151

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_POST_CSC_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

152

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_POST_CSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

153

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_POST_CSC_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1537

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1544

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1546

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1547

dpp->base.funcs = &dcn30_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1548

dpp->base.caps = &dcn30_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1550

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1551

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

1552

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

168

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

178

void dpp3_set_pre_degam(struct dpp *dpp_base, enum dc_transfer_func_predefined tr)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

180

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

221

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

228

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

34

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

37

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

401

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

405

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

41

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

439

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

44

void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

46

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

487

dpp->ctx->dc->debug.max_downscale_src_width != 0 &&

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

488

scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

501

dpp->caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

531

if (!dpp->ctx->dc->debug.always_scale) {

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

549

static void dpp3_deferred_update(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

552

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

597

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

600

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

615

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

618

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

633

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

636

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

651

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

654

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

664

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

669

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

700

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

703

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

704

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

705

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

706

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

707

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

708

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

709

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

710

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

712

reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

713

reg->masks.field_region_end = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

714

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

715

reg->masks.field_region_end_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

716

reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

717

reg->masks.field_region_end_base = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

718

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

719

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

720

reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

721

reg->masks.exp_region_start = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

722

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

723

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_BLNDGAM_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

728

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

731

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

734

dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

751

cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

756

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

759

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

762

dcn3_dpp_cm_get_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

779

cm_helper_program_gamcor_xfer_func(dpp->base.ctx, params, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

782

static enum dc_lut_mode dpp3_get_blndgam_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

788

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

813

static bool dpp3_program_blnd_lut(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

818

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

852

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

860

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

87

void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

883

static enum dc_lut_mode dpp3_get_shaper_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

887

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

89

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

910

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

913

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

925

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c

929

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

30

#define TO_DCN30_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

31

container_of(dpp, struct dcn3_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

561

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

588

struct dpp *dpp_base, const struct pwl_params *params);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

591

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

594

void dpp30_read_state(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

597

void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

600

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

605

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

613

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

617

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

621

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

624

void dpp3_set_pre_degam(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

628

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

632

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

638

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

642

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h

645

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

128

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

131

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

150

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

153

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

161

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

164

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

173

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

177

reg->shifts.field_region_start_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

178

reg->masks.field_region_start_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

179

reg->shifts.field_offset = dpp->tf_shift->CM_GAMCOR_RAMA_OFFSET_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

180

reg->masks.field_offset = dpp->tf_mask->CM_GAMCOR_RAMA_OFFSET_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

182

reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

183

reg->masks.exp_region0_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

184

reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

185

reg->masks.exp_region0_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

186

reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

187

reg->masks.exp_region1_lut_offset = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

188

reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

189

reg->masks.exp_region1_num_segments = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

191

reg->shifts.field_region_end = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

192

reg->masks.field_region_end = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

193

reg->shifts.field_region_end_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

194

reg->masks.field_region_end_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

195

reg->shifts.field_region_end_base = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

196

reg->masks.field_region_end_base = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_END_BASE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

197

reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

198

reg->masks.field_region_linear_slope = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

199

reg->shifts.exp_region_start = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

200

reg->masks.exp_region_start = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

201

reg->shifts.exp_resion_start_segment = dpp->tf_shift->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

202

reg->masks.exp_resion_start_segment = dpp->tf_mask->CM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

206

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

209

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

220

struct dpp *dpp_base, const struct pwl_params *params)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

224

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

294

dpp3_gamcor_reg_field(dpp, &gam_regs);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

309

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

312

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

319

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

34

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

345

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

346

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

347

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

348

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

356

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

366

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

37

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

378

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

381

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

387

program_gamut_remap(dpp, NULL, GAMUT_REMAP_BYPASS);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

409

program_gamut_remap(dpp, arr_reg_val, gamut_mode);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

41

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

413

static void read_gamut_remap(struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

425

gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

426

gam_regs.masks.csc_c11 = dpp->tf_mask->CM_GAMUT_REMAP_C11;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

427

gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

428

gam_regs.masks.csc_c12 = dpp->tf_mask->CM_GAMUT_REMAP_C12;

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

434

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

44

struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

442

cm_helper_read_color_matrices(dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

448

void dpp3_cm_get_gamut_remap(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

451

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

455

read_gamut_remap(dpp, arr_reg_val, &select);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

46

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

57

static enum dc_lut_mode dpp30_get_gamcor_current(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

62

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

78

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c

85

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

148

struct dcn3_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

155

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

157

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

158

dpp->base.funcs = &dcn32_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

159

dpp->base.caps = &dcn32_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

161

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

162

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c

163

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

130

struct dcn3_dpp *dpp, struct dc_context *ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

135

bool ret = dpp32_construct(dpp, ctx, inst, tf_regs,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

139

dpp->base.funcs = &dcn35_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

142

if (dpp->base.ctx->asic_id.hw_internal_rev < 0x40)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

143

dpp->dispclk_r_gate_disable = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

147

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

31

#define REG(reg) dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

33

#define CTX dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

37

((const struct dcn35_dpp_shift *)(dpp->tf_shift))->field_name, \

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

38

((const struct dcn35_dpp_mask *)(dpp->tf_mask))->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

41

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

45

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

48

if (dpp->tf_mask->DPPCLK_RATE_CONTROL)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

53

if (dpp->dispclk_r_gate_disable)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

61

if (dpp->dispclk_r_gate_disable)

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

71

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c

74

struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

53

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

62

void dpp35_set_fgcg(struct dcn3_dpp *dpp, bool enable);

drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.h

64

void dpp35_program_bias_and_scale_fcnv(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

263

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

270

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

272

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

273

dpp->base.funcs = &dcn401_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

274

dpp->base.caps = &dcn401_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

276

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

277

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

278

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

36

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

39

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

43

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

45

void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

47

struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

56

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c

63

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

33

#define TO_DCN401_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

34

container_of(dpp, struct dcn401_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

670

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

706

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

710

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

718

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

722

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

729

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

745

void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.h

748

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

126

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

135

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

148

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

151

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

170

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

174

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

212

cur_matrix_regs.shifts.csc_c11 = dpp->tf_shift->CUR0_MATRIX_C11_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

213

cur_matrix_regs.masks.csc_c11 = dpp->tf_mask->CUR0_MATRIX_C11_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

214

cur_matrix_regs.shifts.csc_c12 = dpp->tf_shift->CUR0_MATRIX_C12_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

215

cur_matrix_regs.masks.csc_c12 = dpp->tf_mask->CUR0_MATRIX_C12_A;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

226

dpp->base.ctx,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

236

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

43

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

46

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

50

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

89

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c

92

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1023

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1037

dpp, scl_data->taps.v_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1044

dpp, scl_data->taps.h_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1070

void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1074

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1090

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1097

(dpp->scl_data.dscl_prog_data.sharpness_level

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1100

dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1101

dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1102

memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1105

if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1110

dpp->scl_data = *scl_data;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1112

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1138

dpp401_dscl_set_recout(dpp, rect);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1157

lb_config = dpp401_dscl_find_lb_memory_config(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1158

dpp401_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

116

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1161

if (dpp->base.ctx->dc->config.prefer_easf)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1181

dpp401_dscl_set_manual_ratio_init(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1199

dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

1201

if (dpp->base.ctx->dc->config.prefer_easf)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

150

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

153

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

155

if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

158

if (dpp->base.ctx->dc->caps.ips_v2_support) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

164

dpp->base.deferred_reg_writes.bits.disable_dscl = false;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

166

if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

167

dpp->base.ctx->dc->optimized_required = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

168

dpp->base.deferred_reg_writes.bits.disable_dscl = true;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

178

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

185

if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

205

if (dpp->base.caps->max_lb_partitions == 31)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

239

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

277

struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

294

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

335

filter_updated = (filter_h && (filter_h != dpp->filter_h))

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

336

|| (filter_v && (filter_v != dpp->filter_v));

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

339

filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

340

|| (filter_v_c && (filter_v_c != dpp->filter_v_c));

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

348

dpp, scl_data->taps.h_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

351

dpp->filter_h = filter_h;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

354

dpp, scl_data->taps.v_taps,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

357

dpp->filter_v = filter_v;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

361

dpp, scl_data->taps.h_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

366

dpp, scl_data->taps.v_taps_c,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

370

dpp->filter_h_c = filter_h_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

371

dpp->filter_v_c = filter_v_c;

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

374

scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

375

dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

44

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

47

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

471

static enum lb_memory_config dpp401_dscl_find_lb_memory_config(struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

480

if (dpp->base.ctx->dc->debug.use_max_lb) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

487

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

494

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

503

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

51

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

511

dpp->base.caps->dscl_calc_lb_num_partitions(

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

523

struct dcn401_dpp *dpp, const struct scaler_data *data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

527

if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) {

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

640

static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

664

static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

666

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

779

static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

781

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

884

static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

886

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

913

static void dpp401_dscl_disable_easf(struct dpp *dpp_base, const struct scaler_data *scl_data)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

915

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

927

struct dcn401_dpp *dpp, const uint32_t *filter)

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

956

static void dpp401_dscl_program_isharp(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c

961

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

119

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

12

dpp->tf_regs->reg

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

126

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

15

dpp->base.ctx

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

19

dpp->tf_shift->field_name, dpp->tf_mask->field_name

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

283

static void dcn42_dpp_force_disable_cursor(struct dpp *dpp_base)

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

285

struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

324

struct dcn42_dpp *dpp,

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

331

dpp->base.ctx = ctx;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

333

dpp->base.inst = inst;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

334

dpp->base.funcs = &dcn42_dpp_funcs;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

335

dpp->base.caps = &dcn42_dpp_cap;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

337

dpp->tf_regs = tf_regs;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

338

dpp->tf_shift = tf_shift;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

339

dpp->tf_mask = tf_mask;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

39

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

43

struct dcn42_dpp *dpp = TO_DCN42_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

71

static bool dpp42_dpp_cm_hist_read(struct dpp *dpp_base, struct cm_hist *hist_out)

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c

73

struct dcn42_dpp *dpp = TO_DCN42_DPP(dpp_base);

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h

10

container_of(dpp, struct dcn42_dpp, base)

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h

445

struct dpp base;

drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.h

9

#define TO_DCN42_DPP(dpp)\

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1491

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1533

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1544

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1550

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1559

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1569

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1576

dpp->funcs->dpp_dppclk_control(dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1587

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1688

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1713

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1719

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1720

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1721

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2082

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2160

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2165

if (dpp == NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2168

dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2172

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2179

&dpp->regamma_params, false)) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2180

dpp->funcs->dpp_program_regamma_pwl(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2181

dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2182

&dpp->regamma_params, OPP_REGAMMA_USER);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2184

dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2189

dpp->regamma_params.hw_points_num);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2838

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2868

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2883

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2899

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2903

if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2904

pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2908

static void dcn10_update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2913

dpp->funcs->dpp_setup(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2922

if (dpp->funcs->dpp_program_bias_and_scale)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2923

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3023

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3024

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3034

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3079

dpp->funcs->dpp_dppclk_control(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3080

dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3087

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3118

dcn10_update_dpp(dpp, plane_state);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3250

pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3251

pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3704

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3921

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3930

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3931

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3942

if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3957

pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

3958

pipe_ctx->plane_res.dpp, &opt_attr);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

469

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

472

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

473

if (dpp->funcs->dpp_get_gamut_remap) {

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

474

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

482

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

528

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

529

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

530

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

531

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

532

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

533

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

534

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

535

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

536

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

537

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

538

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

539

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

540

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

541

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.h

199

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

104

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1065

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1085

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1113

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1284

hws->funcs.dpp_root_clock_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1293

hws->funcs.dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

152

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

153

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

154

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

155

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

156

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

157

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

158

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

159

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1596

if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

160

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

161

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

162

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

163

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

164

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

165

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1682

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1689

dpp->funcs->dpp_dppclk_control(dpp, false, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1692

dccg->funcs->update_dpp_dto(dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1743

dpp->funcs->dpp_setup(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1750

if (dpp->funcs->set_cursor_matrix) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1751

dpp->funcs->set_cursor_matrix(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1755

if (dpp->funcs->dpp_program_bias_and_scale) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1757

dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1777

pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1778

pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3197

struct dpp *dpp = res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3199

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3217

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3223

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3224

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

3225

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

608

struct dpp *dpp5 = hws->ctx->dc->res_pool->dpps[dpp_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

702

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

719

dpp->funcs->dpp_dppclk_control(dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

724

pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

91

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

94

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

95

if (dpp->funcs->dpp_get_gamut_remap) {

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

96

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

291

struct dpp *dpp = res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

293

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

311

struct dpp *dpp = res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

317

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

318

pipe_ctx->plane_res.mpcc_inst = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

319

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

384

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

567

pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(

drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c

568

pipe_ctx->plane_res.dpp, attributes);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

106

dpp->inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1303

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1314

if (dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1315

if (dpp->funcs->dpp_read_reg_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

1316

dpp->funcs->dpp_read_reg_state(dpp, out_data->dpp_reg_state[i]);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

161

dc->caps.color.dpp.input_lut_shared,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

162

dc->caps.color.dpp.icsc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

163

dc->caps.color.dpp.dgam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

164

dc->caps.color.dpp.dgam_rom_caps.srgb,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

165

dc->caps.color.dpp.dgam_rom_caps.bt2020,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

166

dc->caps.color.dpp.dgam_rom_caps.gamma2_2,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

167

dc->caps.color.dpp.dgam_rom_caps.pq,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

168

dc->caps.color.dpp.dgam_rom_caps.hlg,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

169

dc->caps.color.dpp.post_csc,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

170

dc->caps.color.dpp.gamma_corr,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

171

dc->caps.color.dpp.dgam_rom_for_yuv,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

172

dc->caps.color.dpp.hw_3d_lut,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

173

dc->caps.color.dpp.ogam_ram,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

174

dc->caps.color.dpp.ocsc);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

238

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

260

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

322

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

377

pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

92

struct dpp *dpp = pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

95

dpp->funcs->dpp_read_state(dpp, &s);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

97

if (dpp->funcs->dpp_get_gamut_remap) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

98

dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

460

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

559

struct dpp *dpp = hws->ctx->dc->res_pool->dpps[dpp_inst];

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

560

if (dpp && dpp->funcs->dpp_force_disable_cursor)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

561

dpp->funcs->dpp_force_disable_cursor(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

449

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

486

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

535

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1085

if (j == PG_DPP && new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1086

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1088

if (j == PG_MPCC && new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1113

cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1114

new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1115

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1694

if (pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1695

pipe->plane_res.dpp->cursor_offload = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1708

if (pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1709

pipe->plane_res.dpp->cursor_offload = false;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1732

const struct dpp *dpp = pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1736

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1760

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1761

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1762

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1763

p->CNVC_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1766

p->CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_BIAS = dpp->att.fp_scale_bias.bits.fp_bias;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1767

p->CNVC_CUR0_CURSOR0_FP_SCALE_BIAS__CUR0_FP_SCALE = dpp->att.fp_scale_bias.bits.fp_scale;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

490

if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

713

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

738

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

744

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

745

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

746

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

838

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

846

dpp->funcs->dpp_dppclk_control(dpp, false, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

878

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

896

dpp->funcs->dpp_dppclk_control(dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

901

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

927

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

928

if (dpp && dpp->funcs->dpp_force_disable_cursor)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

929

dpp->funcs->dpp_force_disable_cursor(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

989

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

992

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1129

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1296

dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2507

hwss_add_dpp_program_cm_hist(seq_state, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

2977

if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3058

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3072

hws->funcs.dpp_pg_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3078

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3088

hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3096

const struct dpp *dpp = pipe->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3100

if (!top_pipe || !hubp || !dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3124

p->CM_CUR0_CURSOR0_CONTROL__CUR0_ENABLE = dpp->att.cur0_ctl.bits.cur0_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3125

p->CM_CUR0_CURSOR0_CONTROL__CUR0_MODE = dpp->att.cur0_ctl.bits.mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3126

p->CM_CUR0_CURSOR0_CONTROL__CUR0_EXPANSION_MODE = dpp->att.cur0_ctl.bits.expansion_mode;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3127

p->CM_CUR0_CURSOR0_CONTROL__CUR0_ROM_EN = dpp->att.cur0_ctl.bits.cur0_rom_en;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3132

dpp->att.fp_scale_bias_g_y.bits.fp_bias_g_y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3134

dpp->att.fp_scale_bias_g_y.bits.fp_scale_g_y;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3136

dpp->att.fp_scale_bias_rb_crcb.bits.fp_bias_rb_crcb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3138

dpp->att.fp_scale_bias_rb_crcb.bits.fp_scale_rb_crcb;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3148

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3163

hwss_add_dpp_pg_control(seq_state, hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3172

hwss_add_dpp_reset(seq_state, dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3181

hwss_add_dpp_root_clock_control(seq_state, hws, dpp->inst, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3191

int dpp_id = pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3563

hwss_add_dpp_dppclk_control(seq_state, pipe_ctx->plane_res.dpp, false, false);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3567

dc->hwseq->funcs.plane_atomic_power_down_sequence(dc, pipe_ctx->plane_res.dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3638

if (!pipe_ctx->plane_res.dpp || !pipe_ctx->plane_res.hubp || !pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3646

hwss_add_dpp_root_clock_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3654

hwss_add_dpp_pg_control(seq_state, hws, pipe_ctx->plane_res.dpp->inst, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3698

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3704

if (!hubp || !dpp || !plane_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3709

hwss_add_dpp_dppclk_control(seq_state, dpp, false, true);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3713

hwss_add_dccg_update_dpp_dto(seq_state, dccg, dpp->inst, pipe_ctx->plane_res.bw.dppclk_khz);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3751

if (dpp->funcs->set_cursor_matrix) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3752

hwss_add_dpp_set_cursor_matrix(seq_state, dpp, plane_state->color_space,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3757

if (dpp->funcs->dpp_program_bias_and_scale)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3780

hwss_add_dpp_set_scaler(seq_state, pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

4032

hwss_add_dpp_set_hdr_multiplier(seq_state, pipe_ctx->plane_res.dpp, hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

446

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

655

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

118

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h

121

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1008

if (pipe_ctx->plane_res.dpp && pipe_ctx->plane_res.hubp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1011

if (pipe_ctx->plane_res.dpp || pipe_ctx->stream_res.opp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1132

if (j == PG_DPP && new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1133

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1135

if (j == PG_MPCC && new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1160

cur_pipe->plane_res.dpp != new_pipe->plane_res.dpp &&

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1161

new_pipe->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1162

update_state->pg_pipe_res_update[j][new_pipe->plane_res.dpp->inst] = true;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

389

struct dpp *dpp = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

391

if (dpp && dpp->funcs->dpp_cm_hist_control)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

392

dpp->funcs->dpp_cm_hist_control(dpp,

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

567

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

699

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

896

struct dpp *dpp_base = pipe_ctx->plane_res.dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

123

struct dpp *dpp = dc->res_pool->dpps[i];

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

148

dpp->funcs->dpp_reset(dpp);

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

154

pipe_ctx->plane_res.dpp = dpp;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

155

pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/dcn42b/dcn42b_hwseq.c

156

hubp->mpcc_id = dpp->inst;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

200

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2004

struct dpp *dpp, uint32_t hw_mult);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2085

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2164

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2215

struct dpp *dpp);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2278

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2301

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

2322

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

339

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

47

struct dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

596

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

622

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

701

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

712

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

759

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

126

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

129

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer_private.h

68

struct dpp;

drivers/gpu/drm/amd/display/dc/inc/core_types.h

253

struct dpp *dpps[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/inc/core_types.h

392

struct dpp *dpp;

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

227

struct dpp *dpp_base, const struct pwl_params *params);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

229

void (*dpp_set_pre_degam)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

232

void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

236

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

239

void (*dpp_read_state)(struct dpp *dpp, struct dcn_dpp_state *s);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

241

void (*dpp_read_reg_state)(struct dpp *dpp, struct dcn_dpp_reg_state *dpp_reg_state);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

243

void (*dpp_reset)(struct dpp *dpp);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

245

void (*dpp_set_scaler)(struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

249

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

254

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

259

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

263

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

267

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

271

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

275

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

280

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

284

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

288

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

292

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

297

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

301

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

305

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

308

void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

312

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

319

void (*dpp_full_bypass)(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

322

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

326

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

334

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

338

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

342

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

347

struct dpp *dpp);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

349

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

352

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

355

struct dpp *dpp,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

358

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

361

void (*dpp_get_gamut_remap)(struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

364

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

368

void (*dpp_force_disable_cursor)(struct dpp *dpp_base);

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

371

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h

376

struct dpp *dpp_base,

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

231

int dpp[MAX_PIPES];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

308

if (pipe_ctx->plane_res.dpp)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

309

cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1141

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1410

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1411

dc->caps.color.dpp.input_lut_shared = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1412

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1413

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1414

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1415

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1416

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1417

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1418

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1419

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1420

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1421

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1423

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1424

dc->caps.color.dpp.ogam_ram = 1; // RGAM on DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1425

dc->caps.color.dpp.ogam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1426

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1427

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1428

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1429

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1430

dc->caps.color.dpp.ocsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

594

static void dcn10_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

596

kfree(TO_DCN10_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

597

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

600

static struct dpp *dcn10_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

604

struct dcn10_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

607

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

610

dpp1_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

612

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1531

next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1588

secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2221

sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2493

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2494

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2495

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2496

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2497

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2498

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2499

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2500

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2501

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2502

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2503

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2504

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2506

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2507

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2509

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2510

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2511

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2512

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2513

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2514

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

756

void dcn20_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

758

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

759

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

762

struct dpp *dcn20_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

766

struct dcn20_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

769

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

772

if (dpp2_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

774

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

777

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

80

void dcn20_dpp_destroy(struct dpp **dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h

82

struct dpp *dcn20_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1057

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1156

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1157

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1158

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1159

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1160

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1161

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1162

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1163

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1164

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1165

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1166

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1167

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1169

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1170

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1172

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1173

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1174

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1175

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1176

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

1177

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

625

static void dcn201_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

627

kfree(TO_DCN201_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

628

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

631

static struct dpp *dcn201_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

635

struct dcn201_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

638

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

641

if (dpp201_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

643

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c

645

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1469

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1470

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1471

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1472

dc->caps.color.dpp.dgam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1473

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1474

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1475

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1476

dc->caps.color.dpp.dgam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1477

dc->caps.color.dpp.dgam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1478

dc->caps.color.dpp.post_csc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1479

dc->caps.color.dpp.gamma_corr = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1480

dc->caps.color.dpp.dgam_rom_for_yuv = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1482

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1483

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1485

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1486

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1487

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1488

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1489

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1490

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

519

static struct dpp *dcn21_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

523

struct dcn20_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

526

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

529

if (dpp2_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

531

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

534

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

1696

sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2487

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2488

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2489

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2490

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2491

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2492

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2493

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2494

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2495

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2496

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2497

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2498

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2500

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2501

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2503

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2504

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2505

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2506

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2507

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

2508

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

788

static void dcn30_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

790

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

791

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

794

static struct dpp *dcn30_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

798

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

801

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

804

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

806

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c

809

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1487

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1488

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1489

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1490

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1491

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1492

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1493

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1494

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1495

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1496

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1497

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1498

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1500

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1501

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1503

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1504

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1505

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1506

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1507

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

1508

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

713

static void dcn301_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

715

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

716

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

719

static struct dpp *dcn301_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

721

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

724

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

727

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

729

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c

732

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1388

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1389

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1390

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1391

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1392

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1393

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1394

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1395

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1396

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1397

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1398

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1399

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1401

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1402

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1404

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1405

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1406

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1407

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1408

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

1409

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

657

static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

659

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

661

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

664

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

665

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c

668

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1332

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1333

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1334

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1335

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1336

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1337

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1338

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1339

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1340

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1341

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1342

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1343

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1345

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1346

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1348

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1349

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1350

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1351

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1352

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

1353

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

635

static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

637

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

639

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

642

if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

643

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c

646

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2093

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2094

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2095

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2096

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2097

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2098

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2099

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2100

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2101

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2102

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2103

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2104

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2106

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2107

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2109

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2110

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2111

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2112

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2113

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

2114

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

970

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

972

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

973

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

976

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

980

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

983

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

986

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

988

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

991

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1005

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1007

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1008

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1011

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1015

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1018

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1021

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1023

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

1026

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2020

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2021

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2022

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2023

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2024

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2025

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2026

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2027

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2028

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2029

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2030

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2031

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2033

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2034

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2036

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2037

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2038

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2039

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2040

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

2041

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

971

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2065

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2066

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2067

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2068

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2069

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2070

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2071

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2072

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2073

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2074

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2075

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2076

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2078

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2079

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2081

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2082

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2083

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2084

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2085

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

2086

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

969

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

971

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

972

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

975

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

979

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

982

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

985

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

987

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

990

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1939

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1940

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1941

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1942

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1943

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1944

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1945

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1946

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1947

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1948

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1949

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1950

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1952

dc->caps.color.dpp.hw_3d_lut = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1953

dc->caps.color.dpp.ogam_ram = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1955

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1956

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1957

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1958

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1959

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

1960

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

962

static void dcn31_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

964

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

965

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

968

static struct dpp *dcn31_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

972

struct dcn3_dpp *dpp =

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

975

if (!dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

978

if (dpp3_construct(dpp, ctx, inst,

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

980

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

983

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2419

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2420

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2421

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2422

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2423

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2424

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2425

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2426

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2427

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2428

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2429

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2430

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2432

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2433

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2435

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2436

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2437

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2438

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2439

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2440

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

2948

idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3007

free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

3040

free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

988

static void dcn32_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

990

kfree(TO_DCN30_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

991

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

994

static struct dpp *dcn32_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1910

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1911

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1912

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1913

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1914

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1915

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1916

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1917

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1918

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1919

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1920

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1921

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1923

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1924

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1926

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1927

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1928

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1929

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1930

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

1931

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

976

static void dcn321_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

978

kfree(TO_DCN30_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

979

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

982

static struct dpp *dcn321_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2048

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2049

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2050

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2051

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2052

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2053

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2054

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2055

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2056

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2057

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2058

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2059

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2061

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2062

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2064

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2065

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2066

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2067

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2068

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

2069

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

802

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

855

static void dcn35_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

857

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

858

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

861

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

863

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

864

bool success = (dpp != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

876

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

880

dpp,

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

881

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

882

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

886

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2021

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2022

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2023

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2024

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2025

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2026

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2027

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2028

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2029

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2030

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2031

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2032

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2034

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2035

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2037

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2038

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2039

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2040

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2041

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

2042

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

782

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

835

static void dcn35_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

837

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

838

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

841

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

843

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

844

bool success = (dpp != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

856

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

860

dpp,

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

861

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

862

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

866

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2018

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2019

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2020

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2021

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2022

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2023

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2024

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2025

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2026

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2027

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2028

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2029

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2031

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2032

dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2034

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2035

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2036

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2037

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2038

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

2039

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

789

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

842

static void dcn35_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

844

kfree(TO_DCN20_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

845

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

848

static struct dpp *dcn35_dpp_create(struct dc_context *ctx, uint32_t inst)

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

850

struct dcn3_dpp *dpp = kzalloc_obj(struct dcn3_dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

851

bool success = (dpp != NULL);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

863

success = dpp35_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

867

dpp,

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

868

ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

869

return &dpp->base;

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

873

kfree(dpp);

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2100

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2101

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2102

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2103

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2104

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2105

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2106

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2107

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2108

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2109

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2110

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2111

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2113

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2114

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2116

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2117

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2118

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2119

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2120

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

2121

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

978

static void dcn401_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

980

kfree(TO_DCN401_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

981

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

984

static struct dpp *dcn401_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1011

static void dcn42_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1013

kfree(TO_DCN42_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1014

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

1017

static struct dpp *dcn42_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2051

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2052

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2053

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2054

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2055

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2056

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2057

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2058

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2059

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2060

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2061

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2062

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2064

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2065

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2067

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2068

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2069

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2070

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2071

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

2072

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c

763

.dpp = true,

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1046

static void dcn42b_dpp_destroy(struct dpp **dpp)

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1048

kfree(TO_DCN42_DPP(*dpp));

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1049

*dpp = NULL;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

1052

static struct dpp *dcn42b_dpp_create(

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2012

dc->caps.color.dpp.dcn_arch = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2013

dc->caps.color.dpp.input_lut_shared = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2014

dc->caps.color.dpp.icsc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2015

dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2016

dc->caps.color.dpp.dgam_rom_caps.srgb = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2017

dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2018

dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2019

dc->caps.color.dpp.dgam_rom_caps.pq = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2020

dc->caps.color.dpp.dgam_rom_caps.hlg = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2021

dc->caps.color.dpp.post_csc = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2022

dc->caps.color.dpp.gamma_corr = 1;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2023

dc->caps.color.dpp.dgam_rom_for_yuv = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2025

dc->caps.color.dpp.hw_3d_lut = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2026

dc->caps.color.dpp.ogam_ram = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2028

dc->caps.color.dpp.ogam_rom_caps.srgb = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2029

dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2030

dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2031

dc->caps.color.dpp.ogam_rom_caps.pq = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2032

dc->caps.color.dpp.ogam_rom_caps.hlg = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

2033

dc->caps.color.dpp.ocsc = 0;

drivers/gpu/drm/amd/display/dc/resource/dcn42b/dcn42b_resource.c

791

.dpp = false,

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1699

dc_caps->dpp.dcn_arch == 1) {

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1702

dc_caps->dpp.dgam_rom_caps.pq == 1)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1706

dc_caps->dpp.dgam_rom_caps.gamma2_2 == 1)

drivers/gpu/drm/amd/display/modules/color/color_gamma.c

1711

dc_caps->dpp.dgam_rom_caps.hlg == 1)

fs/nfsd/vfs.c

126

nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp,

fs/nfsd/vfs.c

130

struct dentry *dentry = *dpp;

fs/nfsd/vfs.c

173

*dpp = path.dentry;

fs/nfsd/vfs.h

76

int nfsd_cross_mnt(struct svc_rqst *rqstp, struct dentry **dpp,

fs/xfs/libxfs/xfs_dquot_buf.c

496

struct xfs_inode **dpp)

fs/xfs/libxfs/xfs_dquot_buf.c

503

return xfs_metadir_mkdir(mp->m_metadirip, "quota", dpp);

fs/xfs/libxfs/xfs_dquot_buf.c

514

struct xfs_inode **dpp)

fs/xfs/libxfs/xfs_dquot_buf.c

524

dpp);

fs/xfs/libxfs/xfs_quota_defs.h

184

int xfs_dqinode_mkdir_parent(struct xfs_mount *mp, struct xfs_inode **dpp);

fs/xfs/libxfs/xfs_quota_defs.h

185

int xfs_dqinode_load_parent(struct xfs_trans *tp, struct xfs_inode **dpp);

fs/xfs/scrub/parent.c

413

struct xfs_inode **dpp)

fs/xfs/scrub/parent.c

447

*dpp = ip;