drivers/ata/pata_hpt37x.c

948

int dpll, adjust;

drivers/ata/pata_hpt37x.c

951

dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;

drivers/ata/pata_hpt37x.c

953

f_low = (MHz[clock_slot] * 48) / MHz[dpll];

drivers/ata/pata_hpt37x.c

981

if (dpll == 3)

drivers/ata/pata_hpt37x.c

987

MHz[clock_slot], MHz[dpll]);

drivers/ata/pata_hpt3x2n.c

312

int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);

drivers/ata/pata_hpt3x2n.c

319

if ((flags & USE_DPLL) != dpll && alt->qc_active)

drivers/ata/pata_hpt3x2n.c

328

int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);

drivers/ata/pata_hpt3x2n.c

330

if ((flags & USE_DPLL) != dpll) {

drivers/ata/pata_hpt3x2n.c

332

flags |= dpll;

drivers/ata/pata_hpt3x2n.c

335

hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);

drivers/clk/rockchip/clk-px30.c

188

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rk3036.c

140

[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),

drivers/clk/rockchip/clk-rk3128.c

161

[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),

drivers/clk/rockchip/clk-rk3188.c

218

[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),

drivers/clk/rockchip/clk-rk3188.c

229

[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),

drivers/clk/rockchip/clk-rk3228.c

171

[dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),

drivers/clk/rockchip/clk-rk3288.c

228

[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),

drivers/clk/rockchip/clk-rk3308.c

183

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rk3328.c

218

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rk3368.c

134

[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),

drivers/clk/rockchip/clk-rk3399.c

223

[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),

drivers/clk/rockchip/clk-rk3528.c

198

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rk3562.c

141

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rk3568.c

333

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rv1103b.c

107

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rv1108.c

156

[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),

drivers/clk/rockchip/clk-rv1126.c

200

[dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,

drivers/clk/rockchip/clk-rv1126b.c

170

[dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p,

drivers/clk/samsung/clk-exynos5420.c

1469

[dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,

drivers/dpll/dpll_core.c

1014

__dpll_pin_unregister(ref->dpll, pin, ops, priv,

drivers/dpll/dpll_core.c

103

ref_tracker_free(&dpll->refcnt_tracker, tracker);

drivers/dpll/dpll_core.c

1047

__dpll_pin_unregister(ref->dpll, pin, ops, priv, parent);

drivers/dpll/dpll_core.c

107

static void __dpll_device_hold(struct dpll_device *dpll, dpll_tracker *tracker)

drivers/dpll/dpll_core.c

1082

dpll_device_registration_first(struct dpll_device *dpll)

drivers/dpll/dpll_core.c

1086

reg = list_first_entry_or_null((struct list_head *)&dpll->registration_list,

drivers/dpll/dpll_core.c

109

dpll_device_tracker_alloc(dpll, tracker);

drivers/dpll/dpll_core.c

1092

void *dpll_priv(struct dpll_device *dpll)

drivers/dpll/dpll_core.c

1096

reg = dpll_device_registration_first(dpll);

drivers/dpll/dpll_core.c

110

refcount_inc(&dpll->refcount);

drivers/dpll/dpll_core.c

1100

const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll)

drivers/dpll/dpll_core.c

1104

reg = dpll_device_registration_first(dpll);

drivers/dpll/dpll_core.c

1119

void *dpll_pin_on_dpll_priv(struct dpll_device *dpll,

drivers/dpll/dpll_core.c

1125

ref = xa_load(&dpll->pin_refs, pin->pin_idx);

drivers/dpll/dpll_core.c

113

static void __dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker)

drivers/dpll/dpll_core.c

115

dpll_device_tracker_free(dpll, tracker);

drivers/dpll/dpll_core.c

116

if (refcount_dec_and_test(&dpll->refcount)) {

drivers/dpll/dpll_core.c

1164

if (ref->dpll->module == pin->module &&

drivers/dpll/dpll_core.c

1165

ref->dpll->clock_id == pin->clock_id)

drivers/dpll/dpll_core.c

117

ASSERT_DPLL_NOT_REGISTERED(dpll);

drivers/dpll/dpll_core.c

118

WARN_ON_ONCE(!xa_empty(&dpll->pin_refs));

drivers/dpll/dpll_core.c

119

xa_destroy(&dpll->pin_refs);

drivers/dpll/dpll_core.c

120

xa_erase(&dpll_device_xa, dpll->id);

drivers/dpll/dpll_core.c

121

WARN_ON(!list_empty(&dpll->registration_list));

drivers/dpll/dpll_core.c

122

ref_tracker_dir_exit(&dpll->refcnt_tracker);

drivers/dpll/dpll_core.c

123

kfree(dpll);

drivers/dpll/dpll_core.c

272

dpll_xa_ref_dpll_add(struct xarray *xa_dplls, struct dpll_device *dpll,

drivers/dpll/dpll_core.c

282

if (ref->dpll != dpll)

drivers/dpll/dpll_core.c

295

ref->dpll = dpll;

drivers/dpll/dpll_core.c

297

ret = xa_insert(xa_dplls, dpll->id, ref, GFP_KERNEL);

drivers/dpll/dpll_core.c

308

xa_erase(xa_dplls, dpll->id);

drivers/dpll/dpll_core.c

316

__dpll_device_hold(dpll, &reg->tracker);

drivers/dpll/dpll_core.c

325

dpll_xa_ref_dpll_del(struct xarray *xa_dplls, struct dpll_device *dpll,

drivers/dpll/dpll_core.c

333

if (ref->dpll != dpll)

drivers/dpll/dpll_core.c

339

__dpll_device_put(dpll, &reg->tracker);

drivers/dpll/dpll_core.c

363

struct dpll_device *dpll;

drivers/dpll/dpll_core.c

366

dpll = kzalloc_obj(*dpll);

drivers/dpll/dpll_core.c

367

if (!dpll)

drivers/dpll/dpll_core.c

369

refcount_set(&dpll->refcount, 1);

drivers/dpll/dpll_core.c

370

INIT_LIST_HEAD(&dpll->registration_list);

drivers/dpll/dpll_core.c

371

dpll->device_idx = device_idx;

drivers/dpll/dpll_core.c

372

dpll->clock_id = clock_id;

drivers/dpll/dpll_core.c

373

dpll->module = module;

drivers/dpll/dpll_core.c

374

ret = xa_alloc_cyclic(&dpll_device_xa, &dpll->id, dpll, xa_limit_32b,

drivers/dpll/dpll_core.c

377

kfree(dpll);

drivers/dpll/dpll_core.c

380

xa_init_flags(&dpll->pin_refs, XA_FLAGS_ALLOC);

drivers/dpll/dpll_core.c

381

ref_tracker_dir_init(&dpll->refcnt_tracker, 128, "dpll_device");

drivers/dpll/dpll_core.c

383

return dpll;

drivers/dpll/dpll_core.c

405

struct dpll_device *dpll, *ret = NULL;

drivers/dpll/dpll_core.c

409

xa_for_each(&dpll_device_xa, index, dpll) {

drivers/dpll/dpll_core.c

410

if (dpll->clock_id == clock_id &&

drivers/dpll/dpll_core.c

411

dpll->device_idx == device_idx &&

drivers/dpll/dpll_core.c

412

dpll->module == module) {

drivers/dpll/dpll_core.c

413

__dpll_device_hold(dpll, tracker);

drivers/dpll/dpll_core.c

414

ret = dpll;

drivers/dpll/dpll_core.c

439

void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker)

drivers/dpll/dpll_core.c

442

__dpll_device_put(dpll, tracker);

drivers/dpll/dpll_core.c

448

dpll_device_registration_find(struct dpll_device *dpll,

drivers/dpll/dpll_core.c

453

list_for_each_entry(reg, &dpll->registration_list, list) {

drivers/dpll/dpll_core.c

474

int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,

drivers/dpll/dpll_core.c

490

reg = dpll_device_registration_find(dpll, ops, priv);

drivers/dpll/dpll_core.c

503

dpll->type = type;

drivers/dpll/dpll_core.c

504

__dpll_device_hold(dpll, &reg->tracker);

drivers/dpll/dpll_core.c

505

first_registration = list_empty(&dpll->registration_list);

drivers/dpll/dpll_core.c

506

list_add_tail(&reg->list, &dpll->registration_list);

drivers/dpll/dpll_core.c

512

xa_set_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED);

drivers/dpll/dpll_core.c

513

dpll_device_create_ntf(dpll);

drivers/dpll/dpll_core.c

530

void dpll_device_unregister(struct dpll_device *dpll,

drivers/dpll/dpll_core.c

536

ASSERT_DPLL_REGISTERED(dpll);

drivers/dpll/dpll_core.c

537

dpll_device_delete_ntf(dpll);

drivers/dpll/dpll_core.c

538

reg = dpll_device_registration_find(dpll, ops, priv);

drivers/dpll/dpll_core.c

544

__dpll_device_put(dpll, &reg->tracker);

drivers/dpll/dpll_core.c

547

if (!list_empty(&dpll->registration_list)) {

drivers/dpll/dpll_core.c

551

xa_clear_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED);

drivers/dpll/dpll_core.c

62

void dpll_device_notify(struct dpll_device *dpll, unsigned long action)

drivers/dpll/dpll_core.c

65

.dpll = dpll,

drivers/dpll/dpll_core.c

66

.id = dpll->id,

drivers/dpll/dpll_core.c

67

.idx = dpll->device_idx,

drivers/dpll/dpll_core.c

68

.clock_id = dpll->clock_id,

drivers/dpll/dpll_core.c

69

.type = dpll->type,

drivers/dpll/dpll_core.c

842

__dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,

drivers/dpll/dpll_core.c

847

ret = dpll_xa_ref_pin_add(&dpll->pin_refs, pin, ops, priv, cookie);

drivers/dpll/dpll_core.c

850

ret = dpll_xa_ref_dpll_add(&pin->dpll_refs, dpll, ops, priv, cookie);

drivers/dpll/dpll_core.c

854

dpll_pin_create_ntf(pin, dpll->clock_id);

drivers/dpll/dpll_core.c

859

dpll_xa_ref_pin_del(&dpll->pin_refs, pin, ops, priv, cookie);

drivers/dpll/dpll_core.c

876

dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,

drivers/dpll/dpll_core.c

885

(!dpll_device_ops(dpll)->freq_monitor_get ||

drivers/dpll/dpll_core.c

886

!dpll_device_ops(dpll)->freq_monitor_set)) ||

drivers/dpll/dpll_core.c

898

WARN_ON_ONCE(dpll->module != pin->module ||

drivers/dpll/dpll_core.c

899

dpll->clock_id != pin->clock_id)) {

drivers/dpll/dpll_core.c

904

ret = __dpll_pin_register(dpll, pin, ops, priv, NULL);

drivers/dpll/dpll_core.c

91

static void dpll_device_tracker_alloc(struct dpll_device *dpll,

drivers/dpll/dpll_core.c

927

__dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,

drivers/dpll/dpll_core.c

931

dpll_pin_delete_ntf(pin, dpll->clock_id);

drivers/dpll/dpll_core.c

932

dpll_xa_ref_pin_del(&dpll->pin_refs, pin, ops, priv, cookie);

drivers/dpll/dpll_core.c

933

dpll_xa_ref_dpll_del(&pin->dpll_refs, dpll, ops, priv, cookie);

drivers/dpll/dpll_core.c

95

ref_tracker_alloc(&dpll->refcnt_tracker, tracker, GFP_KERNEL);

drivers/dpll/dpll_core.c

950

void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,

drivers/dpll/dpll_core.c

953

if (WARN_ON(xa_empty(&dpll->pin_refs)))

drivers/dpll/dpll_core.c

959

__dpll_pin_unregister(dpll, pin, ops, priv, NULL);

drivers/dpll/dpll_core.c

99

static void dpll_device_tracker_free(struct dpll_device *dpll,

drivers/dpll/dpll_core.c

999

ret = __dpll_pin_register(ref->dpll, pin, ops, priv, parent);

drivers/dpll/dpll_core.h

103

void dpll_device_notify(struct dpll_device *dpll, unsigned long action);

drivers/dpll/dpll_core.h

83

struct dpll_device *dpll;

drivers/dpll/dpll_core.h

90

void *dpll_priv(struct dpll_device *dpll);

drivers/dpll/dpll_core.h

91

void *dpll_pin_on_dpll_priv(struct dpll_device *dpll, struct dpll_pin *pin);

drivers/dpll/dpll_core.h

94

const struct dpll_device_ops *dpll_device_ops(struct dpll_device *dpll);

drivers/dpll/dpll_netlink.c

1006

return ops->mode_set(dpll, dpll_priv(dpll), mode, extack);

drivers/dpll/dpll_netlink.c

1010

dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a,

drivers/dpll/dpll_netlink.c

1013

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

102

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

1021

ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state,

drivers/dpll/dpll_netlink.c

1030

return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state,

drivers/dpll/dpll_netlink.c

1035

dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a,

drivers/dpll/dpll_netlink.c

1038

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

1047

return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor,

drivers/dpll/dpll_netlink.c

1052

dpll_freq_monitor_set(struct dpll_device *dpll, struct nlattr *a,

drivers/dpll/dpll_netlink.c

1055

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

106

ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack);

drivers/dpll/dpll_netlink.c

1064

ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), &old_state,

drivers/dpll/dpll_netlink.c

1074

return ops->freq_monitor_set(dpll, dpll_priv(dpll), state, extack);

drivers/dpll/dpll_netlink.c

1084

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

1096

ref->dpll->module == pin->module &&

drivers/dpll/dpll_netlink.c

1097

ref->dpll->clock_id == pin->clock_id) {

drivers/dpll/dpll_netlink.c

1109

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1110

ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

1111

dpll_priv(dpll), &old_freq, extack);

drivers/dpll/dpll_netlink.c

1123

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1124

ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1125

dpll, dpll_priv(dpll), freq, extack);

drivers/dpll/dpll_netlink.c

1129

dpll->id);

drivers/dpll/dpll_netlink.c

1144

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1145

if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1146

dpll, dpll_priv(dpll), old_freq, extack))

drivers/dpll/dpll_netlink.c

116

dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

1160

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

1168

ref->dpll->module == pin->module &&

drivers/dpll/dpll_netlink.c

1169

ref->dpll->clock_id == pin->clock_id) {

drivers/dpll/dpll_netlink.c

1181

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1182

ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

1183

dpll_priv(dpll), &esync, extack);

drivers/dpll/dpll_netlink.c

119

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

1205

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1206

pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin);

drivers/dpll/dpll_netlink.c

1207

ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

1213

dpll->id);

drivers/dpll/dpll_netlink.c

1230

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1231

pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin);

drivers/dpll/dpll_netlink.c

1232

if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

125

ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes,

drivers/dpll/dpll_netlink.c

1250

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

1274

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1275

ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1277

dpll_pin_on_dpll_priv(dpll, ref_sync_pin),

drivers/dpll/dpll_netlink.c

1289

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1290

ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1292

dpll_pin_on_dpll_priv(dpll,

drivers/dpll/dpll_netlink.c

1298

dpll->id);

drivers/dpll/dpll_netlink.c

1313

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1314

if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1316

dpll_pin_on_dpll_priv(dpll, ref_sync_pin),

drivers/dpll/dpll_netlink.c

133

ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack);

drivers/dpll/dpll_netlink.c

1380

parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent);

drivers/dpll/dpll_netlink.c

1392

dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin,

drivers/dpll/dpll_netlink.c

1408

ref = xa_load(&pin->dpll_refs, dpll->id);

drivers/dpll/dpll_netlink.c

1413

ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1414

dpll, dpll_priv(dpll), state, extack);

drivers/dpll/dpll_netlink.c

1423

dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin,

drivers/dpll/dpll_netlink.c

1435

ref = xa_load(&pin->dpll_refs, dpll->id);

drivers/dpll/dpll_netlink.c

1440

ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

1441

dpll_priv(dpll), prio, extack);

drivers/dpll/dpll_netlink.c

1450

dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

1463

ref = xa_load(&pin->dpll_refs, dpll->id);

drivers/dpll/dpll_netlink.c

1468

ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1469

dpll, dpll_priv(dpll), direction, extack);

drivers/dpll/dpll_netlink.c

148

dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

1484

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

1505

ref->dpll->module == pin->module &&

drivers/dpll/dpll_netlink.c

1506

ref->dpll->clock_id == pin->clock_id) {

drivers/dpll/dpll_netlink.c

151

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

1517

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1518

ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1519

dpll, dpll_priv(dpll), &old_phase_adj,

drivers/dpll/dpll_netlink.c

1532

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1534

dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1535

dpll, dpll_priv(dpll), phase_adj,

drivers/dpll/dpll_netlink.c

1541

dpll->id);

drivers/dpll/dpll_netlink.c

1556

dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

1557

if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

1558

dpll, dpll_priv(dpll), old_phase_adj,

drivers/dpll/dpll_netlink.c

156

ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

1573

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

1584

dpll = xa_load(&dpll_device_xa, pdpll_idx);

drivers/dpll/dpll_netlink.c

1585

if (!dpll) {

drivers/dpll/dpll_netlink.c

1589

ref = xa_load(&pin->dpll_refs, dpll->id);

drivers/dpll/dpll_netlink.c

1596

ret = dpll_pin_state_set(dpll, pin, state, extack);

drivers/dpll/dpll_netlink.c

1602

ret = dpll_pin_prio_set(dpll, pin, prio, extack);

drivers/dpll/dpll_netlink.c

1608

ret = dpll_pin_direction_set(pin, dpll, direction, extack);

drivers/dpll/dpll_netlink.c

168

dpll_msg_add_freq_monitor(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

171

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

176

ret = ops->freq_monitor_get(dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

189

struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

1900

struct dpll_device *dpll_match = NULL, *dpll;

drivers/dpll/dpll_netlink.c

1904

xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) {

drivers/dpll/dpll_netlink.c

1905

cid_match = clock_id ? dpll->clock_id == clock_id : true;

drivers/dpll/dpll_netlink.c

1906

mod_match = mod_name_attr ? (module_name(dpll->module) ?

drivers/dpll/dpll_netlink.c

1908

module_name(dpll->module)) : false) : true;

drivers/dpll/dpll_netlink.c

1909

type_match = type ? dpll->type == type : true;

drivers/dpll/dpll_netlink.c

1915

dpll_match = dpll;

drivers/dpll/dpll_netlink.c

192

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

1968

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

197

ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

1983

dpll = dpll_device_find_from_nlattr(info);

drivers/dpll/dpll_netlink.c

1984

if (IS_ERR(dpll)) {

drivers/dpll/dpll_netlink.c

1986

return PTR_ERR(dpll);

drivers/dpll/dpll_netlink.c

1988

ret = dpll_msg_add_dev_handle(msg, dpll);

drivers/dpll/dpll_netlink.c

2000

struct dpll_device *dpll = info->user_ptr[0];

drivers/dpll/dpll_netlink.c

2015

ret = dpll_device_get_one(dpll, msg, info->extack);

drivers/dpll/dpll_netlink.c

2026

dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info)

drivers/dpll/dpll_netlink.c

2035

ret = dpll_mode_set(dpll, a, info->extack);

drivers/dpll/dpll_netlink.c

2040

ret = dpll_phase_offset_monitor_set(dpll, a,

drivers/dpll/dpll_netlink.c

2046

ret = dpll_phase_offset_avg_factor_set(dpll, a,

drivers/dpll/dpll_netlink.c

2052

ret = dpll_freq_monitor_set(dpll, a,

drivers/dpll/dpll_netlink.c

2065

struct dpll_device *dpll = info->user_ptr[0];

drivers/dpll/dpll_netlink.c

2067

return dpll_set_from_nlattr(dpll, info);

drivers/dpll/dpll_netlink.c

2073

struct dpll_device *dpll;

drivers/dpll/dpll_netlink.c

2079

xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED,

drivers/dpll/dpll_netlink.c

2088

ret = dpll_device_get_one(dpll, skb, cb->extack);

drivers/dpll/dpll_netlink.c

209

dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

212

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

217

ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status,

drivers/dpll/dpll_netlink.c

233

dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

236

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

242

ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack);

drivers/dpll/dpll_netlink.c

252

dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

256

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

262

ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack);

drivers/dpll/dpll_netlink.c

278

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

284

ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

285

dpll_priv(dpll), &prio, extack);

drivers/dpll/dpll_netlink.c

300

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

306

ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

307

dpll, dpll_priv(dpll), &state, extack);

drivers/dpll/dpll_netlink.c

322

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

329

dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

330

dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

34

dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll)

drivers/dpll/dpll_netlink.c

346

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

350

ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

351

dpll_priv(dpll), &direction, extack);

drivers/dpll/dpll_netlink.c

36

if (nla_put_u32(msg, DPLL_A_ID, dpll->id))

drivers/dpll/dpll_netlink.c

366

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

372

ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

373

dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

389

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

395

ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

396

dpll, dpll_priv(dpll), &phase_offset,

drivers/dpll/dpll_netlink.c

418

ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(ref->dpll, pin),

drivers/dpll/dpll_netlink.c

419

ref->dpll, dpll_priv(ref->dpll), &ffo, extack);

drivers/dpll/dpll_netlink.c

437

const struct dpll_device_ops *dev_ops = dpll_device_ops(ref->dpll);

drivers/dpll/dpll_netlink.c

439

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

446

ret = dev_ops->freq_monitor_get(dpll, dpll_priv(dpll),

drivers/dpll/dpll_netlink.c

452

ret = ops->measured_freq_get(pin, dpll_pin_on_dpll_priv(dpll, pin),

drivers/dpll/dpll_netlink.c

453

dpll, dpll_priv(dpll), &measured_freq,

drivers/dpll/dpll_netlink.c

470

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

477

ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

478

dpll_priv(dpll), &freq, extack);

drivers/dpll/dpll_netlink.c

511

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

518

ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,

drivers/dpll/dpll_netlink.c

519

dpll_priv(dpll), &esync, extack);

drivers/dpll/dpll_netlink.c

557

struct dpll_device *dpll = ref->dpll;

drivers/dpll/dpll_netlink.c

565

pin_priv = dpll_pin_on_dpll_priv(dpll, pin);

drivers/dpll/dpll_netlink.c

569

ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin);

drivers/dpll/dpll_netlink.c

623

parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin);

drivers/dpll/dpll_netlink.c

63

if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id,

drivers/dpll/dpll_netlink.c

662

ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id);

drivers/dpll/dpll_netlink.c

769

dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg,

drivers/dpll/dpll_netlink.c

774

ret = dpll_msg_add_dev_handle(msg, dpll);

drivers/dpll/dpll_netlink.c

777

if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module)))

drivers/dpll/dpll_netlink.c

779

if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id),

drivers/dpll/dpll_netlink.c

780

&dpll->clock_id, DPLL_A_PAD))

drivers/dpll/dpll_netlink.c

782

ret = dpll_msg_add_temp(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

785

ret = dpll_msg_add_lock_status(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

788

ret = dpll_msg_add_clock_quality_level(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

791

ret = dpll_msg_add_mode(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

794

ret = dpll_msg_add_mode_supported(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

797

if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type))

drivers/dpll/dpll_netlink.c

799

ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

802

ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

805

ret = dpll_msg_add_freq_monitor(msg, dpll, extack);

drivers/dpll/dpll_netlink.c

813

dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll)

drivers/dpll/dpll_netlink.c

819

if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED)))

drivers/dpll/dpll_netlink.c

827

ret = dpll_device_get_one(dpll, msg, NULL);

drivers/dpll/dpll_netlink.c

843

int dpll_device_create_ntf(struct dpll_device *dpll)

drivers/dpll/dpll_netlink.c

845

dpll_device_notify(dpll, DPLL_DEVICE_CREATED);

drivers/dpll/dpll_netlink.c

846

return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll);

drivers/dpll/dpll_netlink.c

849

int dpll_device_delete_ntf(struct dpll_device *dpll)

drivers/dpll/dpll_netlink.c

851

dpll_device_notify(dpll, DPLL_DEVICE_DELETED);

drivers/dpll/dpll_netlink.c

852

return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll);

drivers/dpll/dpll_netlink.c

863

int __dpll_device_change_ntf(struct dpll_device *dpll)

drivers/dpll/dpll_netlink.c

866

dpll_device_notify(dpll, DPLL_DEVICE_CHANGED);

drivers/dpll/dpll_netlink.c

867

return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll);

drivers/dpll/dpll_netlink.c

878

int dpll_device_change_ntf(struct dpll_device *dpll)

drivers/dpll/dpll_netlink.c

883

ret = __dpll_device_change_ntf(dpll);

drivers/dpll/dpll_netlink.c

971

dpll_mode_set(struct dpll_device *dpll, struct nlattr *a,

drivers/dpll/dpll_netlink.c

974

const struct dpll_device_ops *ops = dpll_device_ops(dpll);

drivers/dpll/dpll_netlink.c

985

ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack);

drivers/dpll/dpll_netlink.c

99

dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll,

drivers/dpll/dpll_netlink.c

994

ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack);

drivers/dpll/dpll_netlink.h

7

int dpll_device_create_ntf(struct dpll_device *dpll);

drivers/dpll/dpll_netlink.h

9

int dpll_device_delete_ntf(struct dpll_device *dpll);

drivers/dpll/zl3073x/dpll.c

1011

zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

1055

zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1078

zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

1108

zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1120

zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1154

zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

1216

zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1232

zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1245

zl3073x_dpll_freq_monitor_get(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

125

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1261

zl3073x_dpll_freq_monitor_set(const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1349

pin->dpll = zldpll;

drivers/dpll/zl3073x/dpll.c

1382

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

1457

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

162

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

1692

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

1750

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

1783

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

1982

struct zl3073x_dev *zldev = pin->dpll->dev;

drivers/dpll/zl3073x/dpll.c

202

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

231

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

297

const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

314

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

329

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

346

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

393

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

449

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

48

struct zl3073x_dpll *dpll;

drivers/dpll/zl3073x/dpll.c

482

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

521

struct zl3073x_dpll *zldpll = pin->dpll;

drivers/dpll/zl3073x/dpll.c

549

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

587

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

600

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

686

const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

698

const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

729

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

787

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

844

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

859

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

933

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

956

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

97

const struct dpll_device *dpll, void *dpll_priv,

drivers/dpll/zl3073x/dpll.c

980

const struct dpll_device *dpll,

drivers/dpll/zl3073x/dpll.c

992

zl3073x_dpll_temp_get(const struct dpll_device *dpll, void *dpll_priv,

drivers/gpu/drm/gma500/cdv_device.c

504

.dpll = DPLL_A,

drivers/gpu/drm/gma500/cdv_device.c

529

.dpll = DPLL_B,

drivers/gpu/drm/gma500/cdv_intel_display.c

585

u32 dpll = 0, dspcntr, pipeconf;

drivers/gpu/drm/gma500/cdv_intel_display.c

666

dpll = DPLL_VGA_MODE_DIS;

drivers/gpu/drm/gma500/cdv_intel_display.c

677

dpll |= DPLL_SYNCLOCK_ENABLE;

drivers/gpu/drm/gma500/cdv_intel_display.c

723

REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);

drivers/gpu/drm/gma500/cdv_intel_display.c

724

REG_READ(map->dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

759

dpll |= DPLL_VCO_ENABLE;

drivers/gpu/drm/gma500/cdv_intel_display.c

768

REG_WRITE(map->dpll,

drivers/gpu/drm/gma500/cdv_intel_display.c

769

(REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/cdv_intel_display.c

770

REG_READ(map->dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

774

if (!(REG_READ(map->dpll) & DPLL_LOCK)) {

drivers/gpu/drm/gma500/cdv_intel_display.c

843

u32 dpll;

drivers/gpu/drm/gma500/cdv_intel_display.c

850

dpll = REG_READ(map->dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

851

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

drivers/gpu/drm/gma500/cdv_intel_display.c

858

dpll = p->dpll;

drivers/gpu/drm/gma500/cdv_intel_display.c

859

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

drivers/gpu/drm/gma500/cdv_intel_display.c

874

ffs((dpll &

drivers/gpu/drm/gma500/cdv_intel_display.c

879

dev_err(dev->dev, "PLL %d\n", dpll);

drivers/gpu/drm/gma500/cdv_intel_display.c

883

if ((dpll & PLL_REF_INPUT_MASK) ==

drivers/gpu/drm/gma500/cdv_intel_display.c

890

if (dpll & PLL_P1_DIVIDE_BY_TWO)

drivers/gpu/drm/gma500/cdv_intel_display.c

894

((dpll &

drivers/gpu/drm/gma500/cdv_intel_display.c

898

if (dpll & PLL_P2_DIVIDE_BY_4)

drivers/gpu/drm/gma500/gma_display.c

223

temp = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

225

REG_WRITE(map->dpll, temp);

drivers/gpu/drm/gma500/gma_display.c

226

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

229

REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/gma_display.c

230

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

233

REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/gma_display.c

234

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

311

temp = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

313

REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/gma_display.c

314

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

595

crtc_state->saveDPLL = REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

634

REG_WRITE(map->dpll,

drivers/gpu/drm/gma500/gma_display.c

636

REG_READ(map->dpll);

drivers/gpu/drm/gma500/gma_display.c

646

REG_WRITE(map->dpll, crtc_state->saveDPLL);

drivers/gpu/drm/gma500/gma_display.c

647

REG_READ(map->dpll);

drivers/gpu/drm/gma500/oaktrail_crtc.c

246

temp = REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

248

REG_WRITE_WITH_AUX(map->dpll, temp, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

249

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

252

REG_WRITE_WITH_AUX(map->dpll,

drivers/gpu/drm/gma500/oaktrail_crtc.c

254

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

257

REG_WRITE_WITH_AUX(map->dpll,

drivers/gpu/drm/gma500/oaktrail_crtc.c

259

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

318

temp = REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

320

REG_WRITE_WITH_AUX(map->dpll,

drivers/gpu/drm/gma500/oaktrail_crtc.c

322

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

374

u32 dpll = 0, fp = 0, dspcntr, pipeconf;

drivers/gpu/drm/gma500/oaktrail_crtc.c

504

dpll = 0; /*BIT16 = 0 for 100MHz reference */

drivers/gpu/drm/gma500/oaktrail_crtc.c

528

dpll |= DPLL_VGA_MODE_DIS;

drivers/gpu/drm/gma500/oaktrail_crtc.c

531

dpll |= DPLL_VCO_ENABLE;

drivers/gpu/drm/gma500/oaktrail_crtc.c

534

dpll |= DPLLA_MODE_LVDS;

drivers/gpu/drm/gma500/oaktrail_crtc.c

536

dpll |= DPLLB_MODE_DAC_SERIAL;

drivers/gpu/drm/gma500/oaktrail_crtc.c

542

dpll |= DPLL_DVO_HIGH_SPEED;

drivers/gpu/drm/gma500/oaktrail_crtc.c

543

dpll |=

drivers/gpu/drm/gma500/oaktrail_crtc.c

551

dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;

drivers/gpu/drm/gma500/oaktrail_crtc.c

553

dpll |= (1 << (clock.p1 - 2)) << 17;

drivers/gpu/drm/gma500/oaktrail_crtc.c

555

dpll |= DPLL_VCO_ENABLE;

drivers/gpu/drm/gma500/oaktrail_crtc.c

557

if (dpll & DPLL_VCO_ENABLE) {

drivers/gpu/drm/gma500/oaktrail_crtc.c

560

REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

561

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

569

REG_WRITE_WITH_AUX(map->dpll, dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

570

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

575

REG_WRITE_WITH_AUX(map->dpll, dpll, i);

drivers/gpu/drm/gma500/oaktrail_crtc.c

576

REG_READ_WITH_AUX(map->dpll, i);

drivers/gpu/drm/gma500/oaktrail_device.c

144

p->dpll = PSB_RVDC32(MRST_DPLL_A);

drivers/gpu/drm/gma500/oaktrail_device.c

261

PSB_WVDC32(p->dpll, MRST_DPLL_A);

drivers/gpu/drm/gma500/oaktrail_device.c

402

.dpll = MRST_DPLL_A,

drivers/gpu/drm/gma500/oaktrail_device.c

426

.dpll = DPLL_B,

drivers/gpu/drm/gma500/oaktrail_hdmi.c

286

u32 dspcntr, pipeconf, dpll, temp;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

296

dpll = REG_READ(DPLL_CTRL);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

297

if ((dpll & DPLL_PWRDN) == 0) {

drivers/gpu/drm/gma500/oaktrail_hdmi.c

298

REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));

drivers/gpu/drm/gma500/oaktrail_hdmi.c

312

dpll = REG_READ(DPLL_CTRL);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

313

dpll &= ~DPLL_PDIV_MASK;

drivers/gpu/drm/gma500/oaktrail_hdmi.c

314

dpll &= ~(DPLL_PWRDN | DPLL_RESET);

drivers/gpu/drm/gma500/oaktrail_hdmi.c

318

REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));

drivers/gpu/drm/gma500/psb_device.c

204

.dpll = DPLL_A,

drivers/gpu/drm/gma500/psb_device.c

228

.dpll = DPLL_B,

drivers/gpu/drm/gma500/psb_drv.h

227

u32 dpll;

drivers/gpu/drm/gma500/psb_drv.h

261

u32 dpll;

drivers/gpu/drm/gma500/psb_intel_display.c

108

u32 dpll = 0, fp = 0, dspcntr, pipeconf;

drivers/gpu/drm/gma500/psb_intel_display.c

159

dpll = DPLL_VGA_MODE_DIS;

drivers/gpu/drm/gma500/psb_intel_display.c

161

dpll |= DPLLB_MODE_LVDS;

drivers/gpu/drm/gma500/psb_intel_display.c

162

dpll |= DPLL_DVO_HIGH_SPEED;

drivers/gpu/drm/gma500/psb_intel_display.c

164

dpll |= DPLLB_MODE_DAC_SERIAL;

drivers/gpu/drm/gma500/psb_intel_display.c

168

dpll |= DPLL_DVO_HIGH_SPEED;

drivers/gpu/drm/gma500/psb_intel_display.c

169

dpll |=

drivers/gpu/drm/gma500/psb_intel_display.c

174

dpll |= (1 << (clock.p1 - 1)) << 16;

drivers/gpu/drm/gma500/psb_intel_display.c

177

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

drivers/gpu/drm/gma500/psb_intel_display.c

180

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

drivers/gpu/drm/gma500/psb_intel_display.c

183

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

drivers/gpu/drm/gma500/psb_intel_display.c

186

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

drivers/gpu/drm/gma500/psb_intel_display.c

193

dpll |= 3;

drivers/gpu/drm/gma500/psb_intel_display.c

195

dpll |= PLL_REF_INPUT_DREFCLK;

drivers/gpu/drm/gma500/psb_intel_display.c

210

dpll |= DPLL_VCO_ENABLE;

drivers/gpu/drm/gma500/psb_intel_display.c

219

if (dpll & DPLL_VCO_ENABLE) {

drivers/gpu/drm/gma500/psb_intel_display.c

221

REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);

drivers/gpu/drm/gma500/psb_intel_display.c

222

REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

256

REG_WRITE(map->dpll, dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

257

REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

262

REG_WRITE(map->dpll, dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

264

REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

311

u32 dpll;

drivers/gpu/drm/gma500/psb_intel_display.c

318

dpll = REG_READ(map->dpll);

drivers/gpu/drm/gma500/psb_intel_display.c

319

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

drivers/gpu/drm/gma500/psb_intel_display.c

326

dpll = p->dpll;

drivers/gpu/drm/gma500/psb_intel_display.c

328

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

drivers/gpu/drm/gma500/psb_intel_display.c

343

ffs((dpll &

drivers/gpu/drm/gma500/psb_intel_display.c

348

if ((dpll & PLL_REF_INPUT_MASK) ==

drivers/gpu/drm/gma500/psb_intel_display.c

355

if (dpll & PLL_P1_DIVIDE_BY_TWO)

drivers/gpu/drm/gma500/psb_intel_display.c

359

((dpll &

drivers/gpu/drm/gma500/psb_intel_display.c

363

if (dpll & PLL_P2_DIVIDE_BY_4)

drivers/gpu/drm/i915/display/g4x_dp.c

34

static const struct dpll g4x_dpll[] = {

drivers/gpu/drm/i915/display/g4x_dp.c

39

static const struct dpll pch_dpll[] = {

drivers/gpu/drm/i915/display/g4x_dp.c

44

static const struct dpll vlv_dpll[] = {

drivers/gpu/drm/i915/display/g4x_dp.c

49

static const struct dpll chv_dpll[] = {

drivers/gpu/drm/i915/display/g4x_dp.c

55

const struct dpll *vlv_get_dpll(struct intel_display *display)

drivers/gpu/drm/i915/display/g4x_dp.c

64

const struct dpll *divisor = NULL;

drivers/gpu/drm/i915/display/g4x_dp.c

84

pipe_config->dpll = divisor[i];

drivers/gpu/drm/i915/display/g4x_dp.h

21

const struct dpll *vlv_get_dpll(struct intel_display *display);

drivers/gpu/drm/i915/display/g4x_dp.h

28

static inline const struct dpll *vlv_get_dpll(struct intel_display *display)

drivers/gpu/drm/i915/display/icl_dsi.c

627

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

633

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

643

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

649

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

679

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/icl_dsi.c

695

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1562

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1572

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1578

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1582

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1857

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1862

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1871

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1876

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1961

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1969

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1977

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

1982

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_ddi.c

3669

if (!intel_encoder_is_tc(encoder) || !display->dpll.mgr)

drivers/gpu/drm/i915/display/intel_display.c

1325

if (display->dpll.mgr) {

drivers/gpu/drm/i915/display/intel_display.c

3138

tmp = pipe_config->dpll_hw_state.i9xx.dpll;

drivers/gpu/drm/i915/display/intel_display.c

5403

if (display->dpll.mgr)

drivers/gpu/drm/i915/display/intel_display.c

5407

if (display->dpll.mgr || HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display.c

8352

struct dpll clock = {

drivers/gpu/drm/i915/display/intel_display.c

8359

u32 dpll, fp;

drivers/gpu/drm/i915/display/intel_display.c

8370

dpll = DPLL_DVO_2X_MODE |

drivers/gpu/drm/i915/display/intel_display.c

8401

dpll & ~DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_display.c

8402

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8413

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display.c

8417

intel_de_write(display, DPLL(display, pipe), dpll);

drivers/gpu/drm/i915/display/intel_display_core.h

637

struct intel_dpll_global dpll;

drivers/gpu/drm/i915/display/intel_display_debugfs.c

643

display->dpll.ref_clks.nssc,

drivers/gpu/drm/i915/display/intel_display_debugfs.c

644

display->dpll.ref_clks.ssc);

drivers/gpu/drm/i915/display/intel_display_types.h

1143

struct dpll dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1004

const struct dpll *clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1005

const struct dpll *reduced_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1008

u32 dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1010

dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;

drivers/gpu/drm/i915/display/intel_dpll.c

1013

dpll |= DPLLB_MODE_LVDS;

drivers/gpu/drm/i915/display/intel_dpll.c

1015

dpll |= DPLLB_MODE_DAC_SERIAL;

drivers/gpu/drm/i915/display/intel_dpll.c

1019

dpll |= (crtc_state->pixel_multiplier - 1)

drivers/gpu/drm/i915/display/intel_dpll.c

1025

dpll |= DPLL_SDVO_HIGH_SPEED;

drivers/gpu/drm/i915/display/intel_dpll.c

1028

dpll |= DPLL_SDVO_HIGH_SPEED;

drivers/gpu/drm/i915/display/intel_dpll.c

1032

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1033

dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1035

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;

drivers/gpu/drm/i915/display/intel_dpll.c

1038

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1044

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

drivers/gpu/drm/i915/display/intel_dpll.c

1047

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

drivers/gpu/drm/i915/display/intel_dpll.c

1050

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

drivers/gpu/drm/i915/display/intel_dpll.c

1053

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

drivers/gpu/drm/i915/display/intel_dpll.c

1059

dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);

drivers/gpu/drm/i915/display/intel_dpll.c

1062

dpll |= PLL_REF_INPUT_TVCLKINBC;

drivers/gpu/drm/i915/display/intel_dpll.c

1065

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

drivers/gpu/drm/i915/display/intel_dpll.c

1067

dpll |= PLL_REF_INPUT_DREFCLK;

drivers/gpu/drm/i915/display/intel_dpll.c

1069

return dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1073

const struct dpll *clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1074

const struct dpll *reduced_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1087

hw_state->dpll = i9xx_dpll(crtc_state, clock, reduced_clock);

drivers/gpu/drm/i915/display/intel_dpll.c

1094

const struct dpll *clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1095

const struct dpll *reduced_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1098

u32 dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1100

dpll = DPLL_VCO_ENABLE | DPLL_VGA_MODE_DIS;

drivers/gpu/drm/i915/display/intel_dpll.c

1103

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1106

dpll |= PLL_P1_DIVIDE_BY_TWO;

drivers/gpu/drm/i915/display/intel_dpll.c

1108

dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1110

dpll |= PLL_P2_DIVIDE_BY_4;

drivers/gpu/drm/i915/display/intel_dpll.c

1129

dpll |= DPLL_DVO_2X_MODE;

drivers/gpu/drm/i915/display/intel_dpll.c

1133

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

drivers/gpu/drm/i915/display/intel_dpll.c

1135

dpll |= PLL_REF_INPUT_DREFCLK;

drivers/gpu/drm/i915/display/intel_dpll.c

1137

return dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1141

const struct dpll *clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1142

const struct dpll *reduced_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1149

hw_state->dpll = i8xx_dpll(crtc_state, clock, reduced_clock);

drivers/gpu/drm/i915/display/intel_dpll.c

1230

static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor)

drivers/gpu/drm/i915/display/intel_dpll.c

1232

return dpll->m < factor * dpll->n;

drivers/gpu/drm/i915/display/intel_dpll.c

1235

static u32 ilk_dpll_compute_fp(const struct dpll *clock, int factor)

drivers/gpu/drm/i915/display/intel_dpll.c

1247

const struct dpll *clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1248

const struct dpll *reduced_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1251

u32 dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1253

dpll = DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_dpll.c

1256

dpll |= DPLLB_MODE_LVDS;

drivers/gpu/drm/i915/display/intel_dpll.c

1258

dpll |= DPLLB_MODE_DAC_SERIAL;

drivers/gpu/drm/i915/display/intel_dpll.c

1260

dpll |= (crtc_state->pixel_multiplier - 1)

drivers/gpu/drm/i915/display/intel_dpll.c

1265

dpll |= DPLL_SDVO_HIGH_SPEED;

drivers/gpu/drm/i915/display/intel_dpll.c

1268

dpll |= DPLL_SDVO_HIGH_SPEED;

drivers/gpu/drm/i915/display/intel_dpll.c

1286

dpll |= DPLL_SDVO_HIGH_SPEED;

drivers/gpu/drm/i915/display/intel_dpll.c

1289

dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1291

dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;

drivers/gpu/drm/i915/display/intel_dpll.c

1295

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;

drivers/gpu/drm/i915/display/intel_dpll.c

1298

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;

drivers/gpu/drm/i915/display/intel_dpll.c

1301

dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;

drivers/gpu/drm/i915/display/intel_dpll.c

1304

dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;

drivers/gpu/drm/i915/display/intel_dpll.c

1311

dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;

drivers/gpu/drm/i915/display/intel_dpll.c

1313

dpll |= PLL_REF_INPUT_DREFCLK;

drivers/gpu/drm/i915/display/intel_dpll.c

1315

return dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1319

const struct dpll *clock,

drivers/gpu/drm/i915/display/intel_dpll.c

1320

const struct dpll *reduced_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

1328

hw_state->dpll = ilk_dpll(crtc_state, clock, reduced_clock);

drivers/gpu/drm/i915/display/intel_dpll.c

1370

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1373

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1375

ilk_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1376

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1382

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1404

u32 dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1406

dpll = DPLL_INTEGRATED_REF_CLK_VLV |

drivers/gpu/drm/i915/display/intel_dpll.c

1410

dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

drivers/gpu/drm/i915/display/intel_dpll.c

1414

dpll |= DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;

drivers/gpu/drm/i915/display/intel_dpll.c

1416

return dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1423

hw_state->dpll = vlv_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1430

u32 dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1432

dpll = DPLL_SSC_REF_CLK_CHV |

drivers/gpu/drm/i915/display/intel_dpll.c

1436

dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;

drivers/gpu/drm/i915/display/intel_dpll.c

1440

dpll |= DPLL_VCO_ENABLE;

drivers/gpu/drm/i915/display/intel_dpll.c

1442

return dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1449

hw_state->dpll = chv_dpll(crtc_state);

drivers/gpu/drm/i915/display/intel_dpll.c

1463

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1466

chv_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1474

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1490

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1493

vlv_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1501

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1540

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1543

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1545

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1546

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1548

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1580

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1583

pnv_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1585

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1586

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1588

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1618

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1621

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1623

i9xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1624

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1626

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1660

refclk, NULL, &crtc_state->dpll))

drivers/gpu/drm/i915/display/intel_dpll.c

1663

i9xx_calc_dpll_params(refclk, &crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1665

i8xx_compute_dpll(crtc_state, &crtc_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll.c

1666

&crtc_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1668

crtc_state->port_clock = crtc_state->dpll.dot;

drivers/gpu/drm/i915/display/intel_dpll.c

1738

ret = display->dpll.funcs->crtc_compute_clock(state, crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1762

if (!display->dpll.funcs->crtc_get_dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

1765

ret = display->dpll.funcs->crtc_get_dpll(state, crtc);

drivers/gpu/drm/i915/display/intel_dpll.c

1779

display->dpll.funcs = &xe3plpd_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1781

display->dpll.funcs = &mtl_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1783

display->dpll.funcs = &dg2_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1785

display->dpll.funcs = &hsw_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1787

display->dpll.funcs = &ilk_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1789

display->dpll.funcs = &chv_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1791

display->dpll.funcs = &vlv_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1793

display->dpll.funcs = &g4x_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1795

display->dpll.funcs = &pnv_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1797

display->dpll.funcs = &i9xx_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1799

display->dpll.funcs = &i8xx_dpll_funcs;

drivers/gpu/drm/i915/display/intel_dpll.c

1833

hw_state->dpll & ~DPLL_VGA_MODE_DIS);

drivers/gpu/drm/i915/display/intel_dpll.c

1834

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1849

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1854

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1893

const struct dpll *clock = &crtc_state->dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

1977

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

1999

hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));

drivers/gpu/drm/i915/display/intel_dpll.c

2001

if (hw_state->dpll & DPLL_VCO_ENABLE) {

drivers/gpu/drm/i915/display/intel_dpll.c

2014

const struct dpll *clock = &crtc_state->dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

2124

intel_de_write(display, DPLL(display, pipe), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll.c

2145

hw_state->dpll & ~DPLL_VCO_ENABLE);

drivers/gpu/drm/i915/display/intel_dpll.c

2147

if (hw_state->dpll & DPLL_VCO_ENABLE) {

drivers/gpu/drm/i915/display/intel_dpll.c

2190

const struct dpll *dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

2201

crtc_state->dpll = *dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

319

static int pnv_calc_dpll_params(int refclk, struct dpll *clock)

drivers/gpu/drm/i915/display/intel_dpll.c

332

static u32 i9xx_dpll_compute_m(const struct dpll *dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

334

return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);

drivers/gpu/drm/i915/display/intel_dpll.c

337

int i9xx_calc_dpll_params(int refclk, struct dpll *clock)

drivers/gpu/drm/i915/display/intel_dpll.c

350

static int vlv_calc_dpll_params(int refclk, struct dpll *clock)

drivers/gpu/drm/i915/display/intel_dpll.c

363

int chv_calc_dpll_params(int refclk, struct dpll *clock)

drivers/gpu/drm/i915/display/intel_dpll.c

381

if ((hw_state->dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)

drivers/gpu/drm/i915/display/intel_dpll.c

410

hw_state->dpll = intel_de_read(display, DPLL(display, crtc->pipe));

drivers/gpu/drm/i915/display/intel_dpll.c

417

hw_state->dpll &= ~(DPLL_LOCK_VLV |

drivers/gpu/drm/i915/display/intel_dpll.c

429

u32 dpll = hw_state->dpll;

drivers/gpu/drm/i915/display/intel_dpll.c

431

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

435

if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)

drivers/gpu/drm/i915/display/intel_dpll.c

451

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>

drivers/gpu/drm/i915/display/intel_dpll.c

454

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>

drivers/gpu/drm/i915/display/intel_dpll.c

457

switch (dpll & DPLL_MODE_MASK) {

drivers/gpu/drm/i915/display/intel_dpll.c

459

clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?

drivers/gpu/drm/i915/display/intel_dpll.c

463

clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?

drivers/gpu/drm/i915/display/intel_dpll.c

469

"mode\n", (int)(dpll & DPLL_MODE_MASK));

drivers/gpu/drm/i915/display/intel_dpll.c

485

clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>

drivers/gpu/drm/i915/display/intel_dpll.c

493

if (dpll & PLL_P1_DIVIDE_BY_TWO)

drivers/gpu/drm/i915/display/intel_dpll.c

496

clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>

drivers/gpu/drm/i915/display/intel_dpll.c

499

if (dpll & PLL_P2_DIVIDE_BY_4)

drivers/gpu/drm/i915/display/intel_dpll.c

524

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

528

if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_dpll.c

551

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

556

if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0)

drivers/gpu/drm/i915/display/intel_dpll.c

584

const struct dpll *clock)

drivers/gpu/drm/i915/display/intel_dpll.c

658

const struct dpll *match_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

659

struct dpll *best_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

662

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

716

const struct dpll *match_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

717

struct dpll *best_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

720

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

772

const struct dpll *match_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

773

struct dpll *best_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

776

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

823

const struct dpll *calculated_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

824

const struct dpll *best_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

866

const struct dpll *match_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

867

struct dpll *best_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

870

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

923

const struct dpll *match_clock,

drivers/gpu/drm/i915/display/intel_dpll.c

924

struct dpll *best_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

928

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll.c

978

struct dpll *best_clock)

drivers/gpu/drm/i915/display/intel_dpll.c

988

u32 i9xx_dpll_compute_fp(const struct dpll *dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

990

return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;

drivers/gpu/drm/i915/display/intel_dpll.c

993

static u32 pnv_dpll_compute_fp(const struct dpll *dpll)

drivers/gpu/drm/i915/display/intel_dpll.c

995

return (1 << dpll->n) << 16 | dpll->m2;

drivers/gpu/drm/i915/display/intel_dpll.h

12

struct dpll;

drivers/gpu/drm/i915/display/intel_dpll.h

24

int i9xx_calc_dpll_params(int refclk, struct dpll *clock);

drivers/gpu/drm/i915/display/intel_dpll.h

25

u32 i9xx_dpll_compute_fp(const struct dpll *dpll);

drivers/gpu/drm/i915/display/intel_dpll.h

32

const struct dpll *dpll);

drivers/gpu/drm/i915/display/intel_dpll.h

42

struct dpll *best_clock);

drivers/gpu/drm/i915/display/intel_dpll.h

43

int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1028

refclk = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1038

refclk = display->dpll.ref_clks.ssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1263

display->dpll.ref_clks.ssc = 135000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1266

display->dpll.ref_clks.nssc = 24000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1268

display->dpll.ref_clks.nssc = 135000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1760

int ref_clock = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

1835

display->dpll.ref_clks.nssc, &wrpll_params);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2001

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2268

static const struct dpll bxt_dp_clk_val[] = {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2281

struct dpll *clk_div)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2299

struct dpll *clk_div)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2312

chv_calc_dpll_params(display->dpll.ref_clks.nssc, clk_div);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2319

const struct dpll *clk_div)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2391

struct dpll clock;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2402

return chv_calc_dpll_params(display->dpll.ref_clks.nssc, &clock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2408

struct dpll clk_div = {};

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2419

struct dpll clk_div = {};

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2476

display->dpll.ref_clks.ssc = 100000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2477

display->dpll.ref_clks.nssc = 100000;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2634

display->dpll.ref_clks.nssc == 38400;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2728

display->dpll.ref_clks.nssc == 24000 ?

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2751

switch (display->dpll.ref_clks.nssc) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2753

MISSING_CASE(display->dpll.ref_clks.nssc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2764

switch (display->dpll.ref_clks.nssc) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2766

MISSING_CASE(display->dpll.ref_clks.nssc);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

2796

int ref_clock = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

286

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3026

int refclk_khz = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

312

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3233

ref_clock = display->dpll.ref_clks.nssc;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

335

mutex_lock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

358

mutex_unlock(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

3645

if (display->dpll.ref_clks.nssc == 38400) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4137

display->dpll.ref_clks.nssc = display->cdclk.hw.ref;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4750

mutex_init(&display->dpll.lock);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4789

i >= ARRAY_SIZE(display->dpll.dplls)))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4796

display->dpll.dplls[i].info = &dpll_info[i];

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4797

display->dpll.dplls[i].index = i;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4800

display->dpll.mgr = dpll_mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4801

display->dpll.num_dpll = i;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4831

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4864

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4887

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4916

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4984

if (display->dpll.mgr && display->dpll.mgr->update_ref_clks)

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

4985

display->dpll.mgr->update_ref_clks(display);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5038

if (display->dpll.mgr) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5039

display->dpll.mgr->dump_hw_state(p, dpll_hw_state);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5062

if (display->dpll.mgr) {

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5063

return display->dpll.mgr->compare_hw_state(a, b);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

5122

const struct intel_dpll_mgr *dpll_mgr = display->dpll.mgr;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

560

hw_state->dpll = val;

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

594

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

605

intel_de_write(display, PCH_DPLL(id), hw_state->dpll);

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

672

hw_state->dpll,

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

684

return a->dpll == b->dpll &&

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

746

if (display->dpll.pch_ssc_use & BIT(id))

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

762

if (display->dpll.pch_ssc_use & BIT(id))

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

184

u32 dpll;

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

33

for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

34

((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++)

drivers/gpu/drm/i915/display/intel_dvo.c

407

u32 dpll[I915_MAX_PIPES];

drivers/gpu/drm/i915/display/intel_dvo.c

446

dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0,

drivers/gpu/drm/i915/display/intel_dvo.c

453

intel_de_write(display, DPLL(display, pipe), dpll[pipe]);

drivers/gpu/drm/i915/display/intel_pch_display.c

538

tmp = crtc_state->dpll_hw_state.i9xx.dpll;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

470

display->dpll.pch_ssc_use = 0;

drivers/gpu/drm/i915/display/intel_pch_refclk.c

474

display->dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

479

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

484

display->dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2);

drivers/gpu/drm/i915/display/intel_pch_refclk.c

487

if (display->dpll.pch_ssc_use)

drivers/gpu/drm/i915/display/intel_sdvo.c

1286

struct dpll *clock = &pipe_config->dpll;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

148

dpll->n = n;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

149

dpll->m = m;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

150

dpll->fdpll = fdpll;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

151

dpll->output = output;

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

163

dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

218

struct dpll_info dpll = { 0 };

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

228

rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

231

| DPLLCR_FDPLL(dpll.fdpll)

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

232

| DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)

drivers/gpu/drm/renesas/rcar-du/rcar_du_crtc.c

84

struct dpll_info *dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

1023

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1036

return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable,

drivers/net/ethernet/intel/ice/ice_dpll.c

1058

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1064

return ice_dpll_pin_state_set(pin, pin_priv, dpll, dpll_priv, enable,

drivers/net/ethernet/intel/ice/ice_dpll.c

1087

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1132

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1136

return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state,

drivers/net/ethernet/intel/ice/ice_dpll.c

1158

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1162

return ice_dpll_pin_state_get(pin, pin_priv, dpll, dpll_priv, state,

drivers/net/ethernet/intel/ice/ice_dpll.c

1293

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1406

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1462

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1526

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1558

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1578

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1597

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1633

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1658

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1685

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1723

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1757

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1791

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1860

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1864

return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1888

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1892

return ice_dpll_pin_phase_adjust_set(pin, pin_priv, dpll, dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1916

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1924

dpll, dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1928

dpll, dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1951

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1963

dpll, dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1968

dpll, dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

1995

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2071

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

211

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2126

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2175

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2230

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2279

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2289

return ice_dpll_input_esync_set(p->input->pin, p->input, dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

2293

dpll, dpll_priv, freq, extack);

drivers/net/ethernet/intel/ice/ice_dpll.c

2315

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

2322

return ice_dpll_input_esync_get(p->input->pin, p->input, dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

2326

dpll, dpll_priv, esync,

drivers/net/ethernet/intel/ice/ice_dpll.c

249

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

252

return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency,

drivers/net/ethernet/intel/ice/ice_dpll.c

2711

const struct dpll_device *dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

274

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

277

return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency,

drivers/net/ethernet/intel/ice/ice_dpll.c

2784

const struct dpll_device *dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

2939

dpll_device_change_ntf(d->dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

300

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

333

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

3341

ice_dpll_unregister_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins,

drivers/net/ethernet/intel/ice/ice_dpll.c

3351

dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]);

drivers/net/ethernet/intel/ice/ice_dpll.c

336

return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency,

drivers/net/ethernet/intel/ice/ice_dpll.c

3399

ice_dpll_register_pins(struct dpll_device *dpll, struct ice_dpll_pin *pins,

drivers/net/ethernet/intel/ice/ice_dpll.c

3406

ret = dpll_pin_register(dpll, pins[i].pin, ops, &pins[i]);

drivers/net/ethernet/intel/ice/ice_dpll.c

3417

dpll_pin_unregister(dpll, pins[i].pin, ops, &pins[i]);

drivers/net/ethernet/intel/ice/ice_dpll.c

358

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

3592

ret = dpll_pin_register(pf->dplls.txc.dpll, pin->pin,

drivers/net/ethernet/intel/ice/ice_dpll.c

361

return ice_dpll_frequency_get(pin, pin_priv, dpll, dpll_priv, frequency,

drivers/net/ethernet/intel/ice/ice_dpll.c

3616

dpll_pin_unregister(pf->dplls.txc.dpll, pin->pin,

drivers/net/ethernet/intel/ice/ice_dpll.c

3795

ice_dpll_unregister_pins(dt->dpll, pf->dplls.txclks,

drivers/net/ethernet/intel/ice/ice_dpll.c

383

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

3833

ice_dpll_unregister_pins(dp->dpll, inputs, &ice_dpll_input_ops,

drivers/net/ethernet/intel/ice/ice_dpll.c

3835

ice_dpll_unregister_pins(de->dpll, inputs, &ice_dpll_input_ops,

drivers/net/ethernet/intel/ice/ice_dpll.c

3840

ice_dpll_unregister_pins(dp->dpll, outputs,

drivers/net/ethernet/intel/ice/ice_dpll.c

3842

ice_dpll_unregister_pins(de->dpll, outputs,

drivers/net/ethernet/intel/ice/ice_dpll.c

3849

pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

3850

pf->dplls.eec.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

3854

pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

3855

pf->dplls.eec.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

394

ret = ice_dpll_input_frequency_set(NULL, sma->input, dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

3977

ret = dpll_pin_register(txc->dpll, ref_pin->pin, &ice_dpll_txclk_ops,

drivers/net/ethernet/intel/ice/ice_dpll.c

398

ret = ice_dpll_output_frequency_set(NULL, sma->output, dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

3998

ret = dpll_pin_register(txc->dpll, ref_pin->pin, &ice_dpll_txclk_ops,

drivers/net/ethernet/intel/ice/ice_dpll.c

4014

dpll_pin_unregister(txc->dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4090

pf->dplls.eec.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4091

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4098

output_ops, pf->dplls.eec.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4099

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4108

pf->dplls.eec.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4109

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4117

pf->dplls.eec.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4118

pf->dplls.pps.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4143

&ice_dpll_pin_ufl_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4144

pf->dplls.eec.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4147

&ice_dpll_pin_sma_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4148

pf->dplls.eec.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4152

output_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4153

pf->dplls.eec.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4157

input_ops, pf->dplls.pps.dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4158

pf->dplls.eec.dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4175

dpll_device_unregister(d->dpll, d->ops, d);

drivers/net/ethernet/intel/ice/ice_dpll.c

4176

dpll_device_put(d->dpll, &d->tracker);

drivers/net/ethernet/intel/ice/ice_dpll.c

4200

d->dpll = dpll_device_get(clock_id, d->dpll_idx, THIS_MODULE,

drivers/net/ethernet/intel/ice/ice_dpll.c

4202

if (IS_ERR(d->dpll)) {

drivers/net/ethernet/intel/ice/ice_dpll.c

4203

ret = PTR_ERR(d->dpll);

drivers/net/ethernet/intel/ice/ice_dpll.c

4216

ret = dpll_device_register(d->dpll, type, ops, d);

drivers/net/ethernet/intel/ice/ice_dpll.c

4218

dpll_device_put(d->dpll, &d->tracker);

drivers/net/ethernet/intel/ice/ice_dpll.c

4219

d->dpll = NULL;

drivers/net/ethernet/intel/ice/ice_dpll.c

423

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

434

ret = ice_dpll_input_frequency_get(NULL, sma->input, dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

438

ret = ice_dpll_output_frequency_get(NULL, sma->output, dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

4858

if (!IS_ERR_OR_NULL(pf->dplls.pps.dpll))

drivers/net/ethernet/intel/ice/ice_dpll.c

4860

if (!IS_ERR_OR_NULL(pf->dplls.eec.dpll))

drivers/net/ethernet/intel/ice/ice_dpll.c

4862

if (!IS_ERR_OR_NULL(pf->dplls.txc.dpll))

drivers/net/ethernet/intel/ice/ice_dpll.c

821

ice_dpll_hw_input_prio_set(struct ice_pf *pf, struct ice_dpll *dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

827

ret = ice_aq_set_cgu_ref_prio(&pf->hw, dpll->dpll_idx, pin->idx,

drivers/net/ethernet/intel/ice/ice_dpll.c

836

dpll->input_prio[pin->idx] = prio;

drivers/net/ethernet/intel/ice/ice_dpll.c

857

ice_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

886

static int ice_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.c

912

static int ice_dpll_phase_offset_monitor_set(const struct dpll_device *dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

943

static int ice_dpll_phase_offset_monitor_get(const struct dpll_device *dpll,

drivers/net/ethernet/intel/ice/ice_dpll.c

980

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/intel/ice/ice_dpll.h

108

struct dpll_device *dpll;

drivers/net/ethernet/intel/ice/ice_txclk.c

333

if (!IS_ERR_OR_NULL(pf->dplls.txc.dpll)) {

drivers/net/ethernet/intel/ice/ice_txclk.c

349

if (notify_dpll && !IS_ERR_OR_NULL(pf->dplls.txc.dpll))

drivers/net/ethernet/intel/ice/ice_txclk.c

350

dpll_device_change_ntf(pf->dplls.txc.dpll);

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

11

struct dpll_device *dpll;

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

146

mlx5_dpll_device_lock_status_get(const struct dpll_device *dpll, void *priv,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

163

static int mlx5_dpll_device_mode_get(const struct dpll_device *dpll,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

200

static int mlx5_dpll_clock_quality_level_get(const struct dpll_device *dpll,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

259

const struct dpll_device *dpll,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

270

const struct dpll_device *dpll,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

288

const struct dpll_device *dpll,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

302

const struct dpll_device *dpll, void *dpll_priv,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

356

dpll_device_change_ntf(mdpll->dpll);

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

445

mdpll->dpll = dpll_device_get(clock_id, 0, THIS_MODULE,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

447

if (IS_ERR(mdpll->dpll)) {

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

448

err = PTR_ERR(mdpll->dpll);

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

452

err = dpll_device_register(mdpll->dpll, DPLL_TYPE_EEC,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

466

err = dpll_pin_register(mdpll->dpll, mdpll->dpll_pin,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

485

dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

490

dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll);

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

492

dpll_device_put(mdpll->dpll, &mdpll->dpll_tracker);

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

506

dpll_pin_unregister(mdpll->dpll, mdpll->dpll_pin,

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

509

dpll_device_unregister(mdpll->dpll, &mlx5_dpll_device_ops, mdpll);

drivers/net/ethernet/mellanox/mlx5/core/dpll.c

510

dpll_device_put(mdpll->dpll, &mdpll->dpll_tracker);

drivers/ptp/ptp_clockmatrix.c

340

u8 dpll = 0;

drivers/ptp/ptp_clockmatrix.c

348

err = read_sys_dpll_status(idtcm, &dpll);

drivers/ptp/ptp_clockmatrix.c

353

dpll &= DPLL_SYS_STATE_MASK;

drivers/ptp/ptp_clockmatrix.c

356

dpll == DPLL_STATE_LOCKED) {

drivers/ptp/ptp_clockmatrix.c

358

} else if (dpll == DPLL_STATE_FREERUN ||

drivers/ptp/ptp_clockmatrix.c

359

dpll == DPLL_STATE_HOLDOVER ||

drivers/ptp/ptp_clockmatrix.c

360

dpll == DPLL_STATE_OPEN_LOOP) {

drivers/ptp/ptp_clockmatrix.c

362

"No wait state: DPLL_SYS_STATE %d", dpll);

drivers/ptp/ptp_clockmatrix.c

371

LOCK_TIMEOUT_MS, apll, dpll);

drivers/ptp/ptp_ocp.c

415

struct dpll_device *dpll;

drivers/ptp/ptp_ocp.c

4909

ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,

drivers/ptp/ptp_ocp.c

4922

const struct dpll_device *dpll, void *priv,

drivers/ptp/ptp_ocp.c

4939

static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,

drivers/ptp/ptp_ocp.c

4948

const struct dpll_device *dpll,

drivers/ptp/ptp_ocp.c

4963

const struct dpll_device *dpll,

drivers/ptp/ptp_ocp.c

4982

const struct dpll_device *dpll,

drivers/ptp/ptp_ocp.c

5004

const struct dpll_device *dpll,

drivers/ptp/ptp_ocp.c

5049

dpll_device_change_ntf(bp->dpll);

drivers/ptp/ptp_ocp.c

5116

bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE, &bp->tracker);

drivers/ptp/ptp_ocp.c

5117

if (IS_ERR(bp->dpll)) {

drivers/ptp/ptp_ocp.c

5118

err = PTR_ERR(bp->dpll);

drivers/ptp/ptp_ocp.c

5123

err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);

drivers/ptp/ptp_ocp.c

5136

err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,

drivers/ptp/ptp_ocp.c

5148

dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);

drivers/ptp/ptp_ocp.c

5151

dpll_device_put(bp->dpll, &bp->tracker);

drivers/ptp/ptp_ocp.c

5171

dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);

drivers/ptp/ptp_ocp.c

5175

dpll_device_unregister(bp->dpll, &dpll_ops, bp);

drivers/ptp/ptp_ocp.c

5176

dpll_device_put(bp->dpll, &bp->tracker);

include/linux/dpll.h

104

const struct dpll_device *dpll,

include/linux/dpll.h

114

const struct dpll_device *dpll,

include/linux/dpll.h

119

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

122

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

125

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

129

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

133

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

137

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

141

const struct dpll_device *dpll,

include/linux/dpll.h

145

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

148

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

222

struct dpll_device *dpll;

include/linux/dpll.h

25

int (*mode_get)(const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

27

int (*mode_set)(const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

280

void dpll_device_put(struct dpll_device *dpll, dpll_tracker *tracker);

include/linux/dpll.h

282

int dpll_device_register(struct dpll_device *dpll, enum dpll_type type,

include/linux/dpll.h

285

void dpll_device_unregister(struct dpll_device *dpll,

include/linux/dpll.h

29

int (*supported_modes_get)(const struct dpll_device *dpll,

include/linux/dpll.h

294

int dpll_pin_register(struct dpll_device *dpll, struct dpll_pin *pin,

include/linux/dpll.h

297

void dpll_pin_unregister(struct dpll_device *dpll, struct dpll_pin *pin,

include/linux/dpll.h

313

int __dpll_device_change_ntf(struct dpll_device *dpll);

include/linux/dpll.h

314

int dpll_device_change_ntf(struct dpll_device *dpll);

include/linux/dpll.h

32

int (*lock_status_get)(const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

36

int (*temp_get)(const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

38

int (*clock_quality_level_get)(const struct dpll_device *dpll,

include/linux/dpll.h

42

int (*phase_offset_monitor_set)(const struct dpll_device *dpll,

include/linux/dpll.h

46

int (*phase_offset_monitor_get)(const struct dpll_device *dpll,

include/linux/dpll.h

50

int (*phase_offset_avg_factor_set)(const struct dpll_device *dpll,

include/linux/dpll.h

53

int (*phase_offset_avg_factor_get)(const struct dpll_device *dpll,

include/linux/dpll.h

56

int (*freq_monitor_set)(const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

59

int (*freq_monitor_get)(const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

79

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

83

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

86

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

90

const struct dpll_device *dpll, void *dpll_priv,

include/linux/dpll.h

99

const struct dpll_device *dpll,