dsi_write
dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
dsi_write(dsi, DSI_CMD_MODE_CFG, val);
dsi_write(dsi, DSI_VID_MODE_CFG, val);
dsi_write(dsi, DSI_GEN_HDR, hdr_val);
dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
dsi_write(dsi, DSI_VID_MODE_CFG, val);
dsi_write(dsi, DSI_PWR_UP, RESET);
dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
dsi_write(dsi, DSI_LPCLK_CTRL, val);
dsi_write(dsi, DSI_PWR_UP, POWERUP);
dsi_write(dsi, DSI_PWR_UP, RESET);
dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
dsi_write(dsi, DSI_PWR_UP, RESET);
dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) |
dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
dsi_write(dsi, DSI_DPI_CFG_POL, val);
dsi_write(dsi, DSI_PCKHDL_CFG, val);
dsi_write(dsi, DSI_VID_PKT_SIZE,
dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(0) | LPRX_TO_CNT(0));
dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
dsi_write(dsi, DSI_PHY_TMR_CFG,
dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
dsi_write(dsi, DSI_PHY_TMR_CFG,
dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
dsi_write(dsi, DSI_INT_MSK0, 0);
dsi_write(dsi, DSI_INT_MSK1, 0);
dsi_write(msm_host, REG_DSI_ACTIVE_H,
dsi_write(msm_host, REG_DSI_ACTIVE_V,
dsi_write(msm_host, REG_DSI_TOTAL,
dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);
dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
dsi_write(msm_host, REG_DSI_RESET, 1);
dsi_write(msm_host, REG_DSI_RESET, 0);
dsi_write(msm_host, REG_DSI_CTRL, ctrl);
dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
dsi_write(msm_host, REG_DSI_STATUS0, status);
dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
dsi_write(msm_host, REG_DSI_CTRL,
dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
dsi_write(msm_host, REG_DSI_DMA_LEN, len);
dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);
dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,
dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
dsi_write(msm_host, REG_DSI_CTRL, 0);
dsi_write(msm_host, REG_DSI_VID_CFG0, data);
dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data);
dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
dsi_write(msm_host, REG_DSI_LANE_CTRL,
dsi_write(msm_host, REG_DSI_CTRL, data);
dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_TESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) |
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR);
dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) |
dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR);
dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);