dsi_read_reg
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
l = dsi_read_reg(dsi, DSI_TIMING1);
r = dsi_read_reg(dsi, DSI_TIMING1);
r = dsi_read_reg(dsi, DSI_VC_CTRL(vc));
val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
dsi_read_reg(dsi, DSI_VC_CTRL(vc));
if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) {
val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(vc));
val = dsi_read_reg(dsi,
r = dsi_read_reg(dsi, DSI_TIMING2);
r = dsi_read_reg(dsi, DSI_TIMING1);
r = dsi_read_reg(dsi, DSI_TIMING1);
r = dsi_read_reg(dsi, DSI_TIMING2);
r = dsi_read_reg(dsi, DSI_CTRL);
r = dsi_read_reg(dsi, DSI_CTRL);
r = dsi_read_reg(dsi, DSI_CTRL);
r = dsi_read_reg(dsi, DSI_VM_TIMING1);
r = dsi_read_reg(dsi, DSI_CLK_TIMING);
r = dsi_read_reg(dsi, DSI_VM_TIMING7);
r = dsi_read_reg(dsi, DSI_CLK_CTRL);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
r = dsi_read_reg(dsi, DSI_VM_TIMING4);
r = dsi_read_reg(dsi, DSI_VM_TIMING5);
r = dsi_read_reg(dsi, DSI_VM_TIMING6);
r = dsi_read_reg(dsi, DSI_CTRL);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
r = dsi_read_reg(dsi, DSI_CLK_TIMING);
r = dsi_read_reg(dsi, DSI_VM_TIMING1);
r = dsi_read_reg(dsi, DSI_VM_TIMING2);
r = dsi_read_reg(dsi, DSI_VM_TIMING3);
irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
dsi_read_reg(dsi, DSI_IRQSTATUS);
vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
rev = dsi_read_reg(dsi, DSI_REVISION);
old_mask = dsi_read_reg(dsi, enable_reg);
dsi_read_reg(dsi, enable_reg);
dsi_read_reg(dsi, status_reg);
FLD_GET(dsi_read_reg(dsi, idx), start, end)
dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
FLD_GET(dsi_read_reg(dsidev, idx), start, end)
dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
l = dsi_read_reg(dsidev, DSI_TIMING1);
r = dsi_read_reg(dsidev, DSI_TIMING1);
r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
val = dsi_read_reg(dsidev,
dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
r = dsi_read_reg(dsidev, DSI_TIMING2);
r = dsi_read_reg(dsidev, DSI_TIMING1);
r = dsi_read_reg(dsidev, DSI_TIMING1);
r = dsi_read_reg(dsidev, DSI_TIMING2);
r = dsi_read_reg(dsidev, DSI_CTRL);
r = dsi_read_reg(dsidev, DSI_CTRL);
r = dsi_read_reg(dsidev, DSI_CTRL);
r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
r = dsi_read_reg(dsidev, DSI_CTRL);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
rev = dsi_read_reg(dsidev, DSI_REVISION);
irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
dsi_read_reg(dsidev, DSI_IRQSTATUS);
vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
old_mask = dsi_read_reg(dsidev, enable_reg);
dsi_read_reg(dsidev, enable_reg);
dsi_read_reg(dsidev, status_reg);