dsi_read
mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
val = dsi_read(dsi, DSI_VID_MODE_CFG);
val = dsi_read(dsi, DSI_GEN_PLD_DATA);
hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
dsi_read(dsi, DSI_INT_ST0);
dsi_read(dsi, DSI_INT_ST1);
ctrl = dsi_read(msm_host, REG_DSI_CTRL);
dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
data = dsi_read(msm_host, REG_DSI_STATUS0);
data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
status = dsi_read(msm_host, REG_DSI_STATUS0);
status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2);
lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
dsi_write(dsi, reg, dsi_read(dsi, reg) | mask);
dsi_write(dsi, reg, dsi_read(dsi, reg) & ~mask);
dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
return dsi_read(dsi, DSI_WRPCR) & WRPCR_PLLEN;
val = dsi_read(dsi, DSI_WRPCR);
dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;