dp_tp_ctl_reg
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
dp_tp_ctl = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
intel_de_posting_read(display, dp_tp_ctl_reg(encoder, crtc_state));
temp = intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state));
intel_de_write(display, dp_tp_ctl_reg(encoder, crtc_state), temp);
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
intel_de_read(display, dp_tp_ctl_reg(encoder, crtc_state)) &
dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
intel_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),
intel_de_rmw(display, dp_tp_ctl_reg(encoder, crtc_state),