drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

209

struct dsc_reg_values dsc_reg_vals;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

33

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

370

bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

517

void dsc_init_reg_values(struct dsc_reg_values *reg_vals)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

521

memset(reg_vals, 0, sizeof(struct dsc_reg_values));

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

573

void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

586

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

567

struct dsc_reg_values reg_vals;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

582

struct dsc_reg_values *dsc_reg_vals,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

590

void dsc_init_reg_values(struct dsc_reg_values *reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

592

void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

12

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

200

static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

323

struct dsc_reg_values reg_vals;