drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

968

struct dc_dsc_config dsc_config;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

984

&dsc_config);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c

986

return dsc_config.bits_per_pixel;

drivers/gpu/drm/amd/display/dc/core/dc.c

3008

if (stream_update->dsc_config)

drivers/gpu/drm/amd/display/dc/core/dc.c

3341

if (update->dsc_config) {

drivers/gpu/drm/amd/display/dc/core/dc.c

3344

uint32_t enable_dsc = (update->dsc_config->num_slices_h != 0 &&

drivers/gpu/drm/amd/display/dc/core/dc.c

3345

update->dsc_config->num_slices_v != 0);

drivers/gpu/drm/amd/display/dc/core/dc.c

3351

stream->timing.dsc_cfg = *update->dsc_config;

drivers/gpu/drm/amd/display/dc/core/dc.c

3357

update->dsc_config = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

3363

update->dsc_config = NULL;

drivers/gpu/drm/amd/display/dc/core/dc.c

3759

if (stream_update->dsc_config)

drivers/gpu/drm/amd/display/dc/core/dc.c

5189

stream_update->dsc_config ||

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2263

struct dsc_config *dsc_cfg = params->dsc_set_config_params.dsc_cfg;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2332

struct dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/dc_stream.h

363

struct dc_dsc_config *dsc_config;

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

167

bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

179

void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

190

void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

206

bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps)

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c

370

bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

573

const struct dsc_config *config);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

581

bool dsc_prepare_config(const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

605

const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

610

bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h

611

void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

113

bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c

124

void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

338

bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.h

339

void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

108

bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

109

void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/dsc/dsc.h

111

bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

84

struct dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1045

struct dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

341

struct dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

228

struct dsc_config *dsc_cfg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

831

struct dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

963

struct dsc_config dsc_cfg;

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1686

struct dsc_config dsc_cfg;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1998

if (hw_dsc->ops.dsc_config)

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

1999

hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, initial_lines);

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c

210

c->ops.dsc_config = dpu_hw_dsc_config;

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h

36

void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c

366

ops->dsc_config = dpu_hw_dsc_config_1_2;