drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2320

struct pipe_ctx *pipe_ctx = params->dsc_calculate_and_set_config_params.pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2322

bool enable = params->dsc_calculate_and_set_config_params.enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2323

int opp_cnt = params->dsc_calculate_and_set_config_params.opp_cnt;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

2350

&params->dsc_calculate_and_set_config_params.dsc_optc_cfg);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3166

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.pipe_ctx = pipe_ctx;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3167

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.enable = enable;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

3168

seq_state->steps[*seq_state->num_steps].params.dsc_calculate_and_set_config_params.opp_cnt = opp_cnt;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1691

&seq_state->steps[last_dsc_calc].params.dsc_calculate_and_set_config_params.dsc_optc_cfg, true);

drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h

772

struct dsc_calculate_and_set_config_params dsc_calculate_and_set_config_params;