drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1310

struct dmub_srv *dmub_srv = adev->dm.dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1323

if (!dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1339

if (dmub_srv->hw_funcs.init_reg_offsets)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1340

dmub_srv->hw_funcs.init_reg_offsets(dmub_srv, ctx);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1342

status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1354

status = dmub_srv_hw_reset(dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

13761

if (adev->dm.dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14024

if (dc->ctx->dmub_srv && !dc->ctx->dmub_srv->idle_exit_counter)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14056

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14057

ctx->dmub_srv->reg_helper_offload.gather_in_progress &&

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14058

!ctx->dmub_srv->reg_helper_offload.should_burst_write) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14234

return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

14242

return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1443

status = dmub_srv_hw_init(dmub_srv, &hw_params);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1450

status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1460

if (!adev->dm.dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1461

adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1462

if (!adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1498

struct dmub_srv *dmub_srv = adev->dm.dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1503

if (!dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1508

status = dmub_srv_is_hw_init(dmub_srv, &init);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1514

status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2470

dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2662

struct dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2754

adev->dm.dmub_srv = kzalloc_obj(*adev->dm.dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2755

dmub_srv = adev->dm.dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2757

if (!dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2769

status = dmub_srv_create(dmub_srv, &create_params);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2807

status = dmub_srv_calc_region_info(dmub_srv, &region_params,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2844

status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2897

if (adev->dm.dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2898

dmub_srv_destroy(adev->dm.dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2899

kfree(adev->dm.dmub_srv);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2900

adev->dm.dmub_srv = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2948

struct dmub_srv *dmub = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2954

!adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

2958

dmub = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3030

} else if (adev->dm.dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3547

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3792

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3825

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3885

dc_dmub_srv_set_power_state(dm->dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

4382

if (dc->caps.ips_support && dc->ctx->dmub_srv->idle_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5032

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

5438

if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

360

struct dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

87

struct dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1035

if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

1037

(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

2698

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3497

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

3541

struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

925

if (adev->dm.dmub_srv)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c

926

fw_meta_info = &adev->dm.dmub_srv->meta_info;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

100

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub ||

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c

101

!dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1067

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

1069

enable_lvtma_control_dmcub(bp->base.ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

180

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

182

encoder_control_dmcub(bp->base.ctx->dmub_srv, &params);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

196

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

296

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

298

transmitter_control_dmcub(bp->base.ctx->dmub_srv, &ps.param);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

382

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

412

transmitter_control_dmcub_v1_7(bp->base.ctx->dmub_srv, &dig_v1_7);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

431

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

559

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

561

set_pixel_clock_dmcub(bp->base.ctx->dmub_srv, &clk);

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

575

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

870

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

872

enable_disp_power_gating_dmcub(bp->base.ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/bios/command_table2.c

888

if (bp->base.ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/core/dc.c

1239

memcpy(color, &dc->ctx->dmub_srv->dmub->visual_confirm_color, sizeof(struct tg_color));

drivers/gpu/drm/amd/display/dc/core/dc.c

1592

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);

drivers/gpu/drm/amd/display/dc/core/dc.c

2412

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, context->stream_mask);

drivers/gpu/drm/amd/display/dc/core/dc.c

3853

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

3905

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

4853

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

492

dc_stream_forward_dmub_crc_window(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

512

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

5122

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

5194

dc_dmub_srv_notify_stream_mask(dc->ctx->dmub_srv, current_stream_mask);

drivers/gpu/drm/amd/display/dc/core/dc.c

530

struct dc_dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

550

dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

553

if (dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

554

dc_stream_forward_dmub_crc_window(dmub_srv, rect, &mux_mapping, is_stop);

drivers/gpu/drm/amd/display/dc/core/dc.c

565

dc_stream_forward_dmub_multiple_crc_window(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/core/dc.c

589

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);

drivers/gpu/drm/amd/display/dc/core/dc.c

596

struct dc_dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

615

dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc.c

618

if (dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

619

dc_stream_forward_dmub_multiple_crc_window(dmub_srv, window, &mux_mapping, stop);

drivers/gpu/drm/amd/display/dc/core/dc.c

6239

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

6250

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D3);

drivers/gpu/drm/amd/display/dc/core/dc.c

6259

dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);

drivers/gpu/drm/amd/display/dc/core/dc.c

6435

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc.c

6438

return dc->ctx->dmub_srv->idle_allowed;

drivers/gpu/drm/amd/display/dc/core/dc.c

6656

dmub_enable_outbox_notification(dc_ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

6995

dc_dmub_srv_log_diagnostic_data(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc.c

7859

dc_dmub_srv_log_preos_dmcub_info(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

1047

block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

646

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !vba)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

719

if (!dc->ctx || !dc->ctx->dmub_srv || !pipe_ctx || !context || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

893

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c

989

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

55

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/core/dc_stat.c

85

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

336

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/core/dc_stream.c

487

if (dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

109

struct dmub_srv *dmub = dc_dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1164

bool dc_dmub_check_min_version(struct dmub_srv *srv)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1173

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1206

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

122

struct dmub_srv *dmub = dc_dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1351

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1354

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

136

struct dmub_srv *dmub = dc_dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1380

dc_dmub_srv_wait_for_idle(dc->ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1472

if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1475

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

152

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1559

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1567

dmub_srv_sync_inboxes(dc->ctx->dmub_srv->dmub);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1590

if (!dc_dmub_srv_is_hw_pwr_up(dc->ctx->dmub_srv, true))

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1603

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1674

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1731

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1764

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1791

struct dc_dmub_srv *dc_dmub_srv = ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1882

struct dmub_fams2_config_v2 *config = (struct dmub_fams2_config_v2 *)dc->ctx->dmub_srv->dmub->ib_mem_gart.cpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

1892

cmd.ib_fams2_config.ib_data.src.quad_part = dc->ctx->dmub_srv->dmub->ib_mem_gart.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

194

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2088

dmub_flush_buffer_mem(&ctx->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2095

cmd.ips_query_residency_info.info_data.dest.quad_part = ctx->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2105

memcpy(driver_info, ctx->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2127

lsdma_data->u.init_data.gpu_addr_base.quad_part = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2128

lsdma_data->u.init_data.ring_size = dc_ctx->dmub_srv->dmub->lsdma_rb_fb.size;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2363

return dc->ctx->dmub_srv && dc->ctx->dmub_srv->cursor_offload_enabled;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2373

if (!dc || !dc->ctx || !dc->ctx->dmub_srv || size == 0)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2376

dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2395

struct dc_dmub_srv *dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

2413

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

272

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

322

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

354

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

376

struct dmub_srv *dmub = dc->ctx->dmub_srv->dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

47

struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

562

memcpy(&dc->ctx->dmub_srv->dmub->visual_confirm_color,

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

60

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

75

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

77

if (*dmub_srv) {

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

78

kfree(*dmub_srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

79

*dmub_srv = NULL;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c

85

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

104

bool dc_dmub_check_min_version(struct dmub_srv *srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

32

struct dmub_srv;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

49

struct dmub_srv *dmub;

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

94

void dc_dmub_srv_clear_inbox0_ack(struct dc_dmub_srv *dmub_srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

95

void dc_dmub_srv_wait_for_inbox0_ack(struct dc_dmub_srv *dmub_srv);

drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h

96

void dc_dmub_srv_send_inbox0_cmd(struct dc_dmub_srv *dmub_srv, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dc/dc_helper.c

147

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

172

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

211

struct dc_reg_helper_state *offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

238

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

239

ctx->dmub_srv->reg_helper_offload.gather_in_progress)

drivers/gpu/drm/amd/display/dc/dc_helper.c

268

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

269

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

437

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

438

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

495

if (ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dc_helper.c

496

ctx->dmub_srv->reg_helper_offload.gather_in_progress) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

634

if (ctx->dmub_srv && ctx->dc->debug.dmub_offload_enabled) {

drivers/gpu/drm/amd/display/dc/dc_helper.c

636

&ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

649

if (!ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_helper.c

652

offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

678

if (!ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dc_helper.c

681

offload = &ctx->dmub_srv->reg_helper_offload;

drivers/gpu/drm/amd/display/dc/dc_helper.c

686

dc_dmub_srv_wait_for_idle(ctx->dmub_srv, DM_DMUB_WAIT_TYPE_WAIT, NULL);

drivers/gpu/drm/amd/display/dc/dc_types.h

878

struct dc_dmub_srv *dmub_srv;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

169

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

172

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)src, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

178

cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

230

dmub_flush_buffer_mem(&dc->dmub_srv->dmub->scratch_mem_fb);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

233

memcpy(dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, (void *)pData, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

239

cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;

drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c

250

memcpy((void *)pData, dc->dmub_srv->dmub->scratch_mem_fb.cpu_addr, bytes);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

110

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

33

return dc->ctx && dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

36

dc->ctx->dmub_srv->dmub->meta_info.feature_bits.bits.inbox0_lock_support;

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

39

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

58

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

61

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

67

dc_dmub_srv_clear_inbox0_ack(dmub_srv);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

68

dc_dmub_srv_send_inbox0_cmd(dmub_srv, data);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.c

69

dc_dmub_srv_wait_for_inbox0_ack(dmub_srv);

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

32

void dmub_hw_lock_mgr_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_hw_lock_mgr.h

37

void dmub_hw_lock_mgr_inbox0_cmd(struct dc_dmub_srv *dmub_srv,

drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c

39

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv)

drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.c

51

dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dce/dmub_outbox.h

31

void dmub_enable_outbox_notification(struct dc_dmub_srv *dmub_srv);

drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c

199

dc_wake_and_execute_dmub_cmd(dc->dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

44

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c

71

struct dc_dmub_srv *dc_dmub_srv = panel_cntl->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c

116

struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/dm_services.h

127

struct dc_dmub_srv *dc_dmub_srv_create(struct dc *dc, struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dc/dm_services.h

128

void dc_dmub_srv_destroy(struct dc_dmub_srv **dmub_srv);

drivers/gpu/drm/amd/display/dc/dm_services.h

41

struct dmub_srv;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

1075

if (ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

917

if (ctx->dc->ctx->dmub_srv &&

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1833

if (!dc_dmub_srv_optimized_init_done(dc->ctx->dmub_srv))

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

2303

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1466

dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

1861

params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

831

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

832

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

833

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

969

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

276

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

277

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

278

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

451

if (!dc_dmub_srv_is_restore_required(dc->ctx->dmub_srv))

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1000

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1001

dc->caps.dmub_caps.subvp_psr = dc->ctx->dmub_srv->dmub->feature_caps.subvp_psr_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1002

dc->caps.dmub_caps.gecc_enable = dc->ctx->dmub_srv->dmub->feature_caps.gecc_enable;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1003

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1004

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1007

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1011

} else if (dc->ctx->dmub_srv->dmub->fw_version <

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

268

if (!dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

357

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

424

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

442

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

998

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

999

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1677

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1700

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1718

shared_stream = &dc->ctx->dmub_srv->dmub->shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1]

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1729

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

271

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

315

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

316

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

317

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

318

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

319

dc->caps.dmub_caps.aux_backlight_support = dc->ctx->dmub_srv->dmub->feature_caps.abm_aux_backlight_support;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1354

if (!dc->ctx->dmub_srv || !dc->current_state)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1567

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1577

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1592

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1602

if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1869

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1891

if (dc->ctx->dmub_srv && dc->debug.fams2_config.bits.enable)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3093

volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

3858

hwss_add_dmub_subvp_save_surf_addr(seq_state, dc->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

387

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

388

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

389

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

390

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

391

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1491

if (!dc->ctx || !dc->ctx->dmub_srv)

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1504

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

1519

dmub_hw_lock_mgr_inbox0_cmd(dc->ctx->dmub_srv, hw_lock_cmd);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

272

if (dc->ctx->dmub_srv) {

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

273

dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv);

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

274

dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

275

dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver > 0;

drivers/gpu/drm/amd/display/dc/hwss/dcn42/dcn42_hwseq.c

276

dc->caps.dmub_caps.fams_ver = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver;

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

863

dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

911

dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1512

if (!link->ctx->dmub_srv ||

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

117

struct dc_dmub_srv *dmub_srv = link->ctx->dmub_srv;

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c

126

if (dc_wake_and_execute_dmub_cmd(dmub_srv->ctx, &cmd,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1002

enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1016

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1028

enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1043

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1055

void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1068

enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1078

void dmub_srv_cmd_get_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1091

enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1108

enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1122

enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

1132

bool dmub_srv_get_preos_info(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

454

void (*init)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

456

void (*reset)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

458

void (*reset_release)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

460

void (*backdoor_load)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

464

void (*backdoor_load_zfb_mode)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

467

void (*setup_windows)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

475

void (*setup_mailbox)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

478

uint32_t (*get_inbox1_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

480

uint32_t (*get_inbox1_rptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

482

void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

484

void (*setup_out_mailbox)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

487

uint32_t (*get_outbox1_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

489

void (*set_outbox1_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

491

void (*setup_outbox0)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

494

uint32_t (*get_outbox0_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

496

void (*set_outbox0_rptr)(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

498

uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

500

uint32_t (*emul_get_inbox1_wptr)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

502

void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

504

bool (*is_supported)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

506

bool (*is_psrsu_supported)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

508

bool (*is_hw_init)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

509

bool (*is_hw_powered_up)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

511

void (*enable_dmub_boot_options)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

514

void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

516

union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

518

union dmub_fw_boot_options (*get_fw_boot_option)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

520

void (*set_gpint)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

523

bool (*is_gpint_acked)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

526

uint32_t (*get_gpint_response)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

528

uint32_t (*get_gpint_dataout)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

530

void (*configure_dmub_in_system_memory)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

531

void (*clear_inbox0_ack_register)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

532

uint32_t (*read_inbox0_ack_register)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

533

void (*send_inbox0_cmd)(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

534

uint32_t (*get_current_time)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

536

void (*get_diagnostic_data)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

537

bool (*get_preos_fw_info)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

539

bool (*should_detect)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

540

void (*init_reg_offsets)(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

542

void (*subvp_save_surf_addr)(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

544

void (*send_reg_inbox0_cmd_msg)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

546

uint32_t (*read_reg_inbox0_rsp_int_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

547

void (*read_reg_inbox0_cmd_rsp)(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

549

void (*write_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

550

void (*clear_reg_inbox0_rsp_int_ack)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

551

void (*enable_reg_inbox0_rsp_int)(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

553

uint32_t (*read_reg_outbox0_rdy_int_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

554

void (*write_reg_outbox0_rdy_int_ack)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

555

void (*read_reg_outbox0_msg)(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

556

void (*write_reg_outbox0_rsp)(struct dmub_srv *dmub, uint32_t *rsp);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

557

uint32_t (*read_reg_outbox0_rsp_int_status)(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

558

void (*enable_reg_outbox0_rdy_int)(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

683

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

690

void dmub_srv_destroy(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

706

dmub_srv_calc_region_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

723

enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

740

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

750

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

765

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

781

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

796

enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

80

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

809

enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

824

enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

827

bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

845

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

864

enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

881

enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

898

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

920

dmub_srv_send_gpint_command(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

937

enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

953

enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

976

enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

979

enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

982

enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

985

bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

987

bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

989

bool dmub_srv_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/dmub_srv_stat.h

38

enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

146

void dmub_dcn20_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

154

void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

189

void dmub_dcn20_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

275

void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

287

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

292

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

297

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

302

void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

314

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

323

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

332

void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

340

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

345

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

350

bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

359

bool dmub_dcn20_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

368

void dmub_dcn20_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

374

bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

385

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

390

union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

398

void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

406

void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

414

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

419

void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

60

static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

87

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c

94

void dmub_dcn20_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

185

void dmub_dcn20_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

187

void dmub_dcn20_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

189

void dmub_dcn20_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

191

void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

195

void dmub_dcn20_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

203

void dmub_dcn20_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

206

uint32_t dmub_dcn20_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

208

uint32_t dmub_dcn20_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

210

void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

212

void dmub_dcn20_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

215

uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

217

void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

219

void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

222

uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

224

void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

226

bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

228

bool dmub_dcn20_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

230

void dmub_dcn20_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

233

bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

236

uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

238

void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

240

void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

242

union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

244

bool dmub_dcn20_use_cached_inbox(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

246

bool dmub_dcn20_use_cached_trace_buffer(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

248

uint32_t dmub_dcn20_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

250

void dmub_dcn20_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

122

void dmub_dcn30_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

60

static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c

87

void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h

37

void dmub_dcn30_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h

41

void dmub_dcn30_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

149

void dmub_dcn31_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

157

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

190

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

246

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

253

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

258

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

263

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

268

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

275

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

284

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

293

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

304

bool dmub_dcn31_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

313

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

318

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

324

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

335

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

340

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

355

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

363

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

371

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

390

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

398

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

406

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

411

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

416

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

421

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

499

bool dmub_dcn31_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

56

static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

83

void dmub_dcn31_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

187

void dmub_dcn31_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

189

void dmub_dcn31_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

191

void dmub_dcn31_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

193

void dmub_dcn31_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

197

void dmub_dcn31_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

205

void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

208

uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

210

uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

212

void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

214

void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

217

uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

219

void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

221

bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

223

bool dmub_dcn31_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

225

bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

227

void dmub_dcn31_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

230

bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

233

uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

235

uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

237

void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

239

void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

241

union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

243

union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

245

void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

248

uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

250

void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

252

uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

254

void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

256

bool dmub_dcn31_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.c

64

bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn314.h

33

bool dmub_dcn314_is_psrsu_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

157

void dmub_dcn32_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

165

void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

200

void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

232

void dmub_dcn32_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

288

void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

295

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

300

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

305

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

310

void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

317

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

326

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

335

bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

346

bool dmub_dcn32_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

355

void dmub_dcn32_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

361

bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

372

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

377

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

392

union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

40

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

400

void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

409

void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

417

void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

425

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

430

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

435

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

440

void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

512

void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

525

void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

530

void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

535

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

540

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

62

static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c

89

void dmub_dcn32_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

198

void dmub_dcn32_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

200

void dmub_dcn32_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

202

void dmub_dcn32_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

206

void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

210

void dmub_dcn32_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

218

void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

221

uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

223

uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

225

void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

227

void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

230

uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

232

void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

234

bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

236

bool dmub_dcn32_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

238

void dmub_dcn32_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

241

bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

244

uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

246

uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

248

void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

250

void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

252

union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

254

void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

257

uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

259

void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

261

uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

263

void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

265

void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

266

void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

267

void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

268

uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

269

void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

271

void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

148

void dmub_dcn35_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

162

void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

193

void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

217

void dmub_dcn35_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

281

void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

288

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

293

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

298

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

303

void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

310

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

319

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

328

bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

339

bool dmub_dcn35_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

348

void dmub_dcn35_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

354

bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

365

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

370

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

385

union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

393

union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

40

void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) {

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

401

void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

430

void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

438

void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

446

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

451

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

456

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

461

void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

534

bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

572

void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

585

bool dmub_dcn35_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

59

static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

592

void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

597

void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

602

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

607

bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c

88

void dmub_dcn35_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

203

void dmub_dcn35_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

205

void dmub_dcn35_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

207

void dmub_dcn35_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

209

void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

213

void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

217

void dmub_dcn35_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

225

void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

228

uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

230

uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

232

void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

234

void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

237

uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

239

void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

241

bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

243

bool dmub_dcn35_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

245

void dmub_dcn35_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

248

bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

251

uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

253

uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

255

void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

257

void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

259

union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

261

union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

263

void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

266

uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

268

void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

270

uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

272

void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

274

void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

276

void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

278

void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

280

uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

282

bool dmub_dcn35_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

284

bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

286

void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

288

bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c

16

void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h

11

void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.h

9

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.c

16

void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h

11

void dmub_srv_dcn36_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn36.h

9

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

131

void dmub_dcn401_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

139

void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

175

void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

208

void dmub_dcn401_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

272

void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

279

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

284

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

289

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

294

void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

301

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

310

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

319

bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

330

bool dmub_dcn401_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

339

void dmub_dcn401_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

345

bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

356

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

36

static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

361

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

376

union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

384

void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

395

void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

403

void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

411

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

416

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

421

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

426

void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

506

void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

519

void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

524

void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

529

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

534

void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

603

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

611

void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

63

void dmub_dcn401_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

636

void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

641

void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

646

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

651

void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

657

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

662

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

667

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

675

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c

680

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

10

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

202

void dmub_dcn401_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

204

void dmub_dcn401_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

206

void dmub_dcn401_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

210

void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

214

void dmub_dcn401_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

222

void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

225

uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

227

uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

229

void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

231

void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

234

uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

236

void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

238

bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

240

bool dmub_dcn401_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

242

void dmub_dcn401_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

245

bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

248

uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

250

uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

252

void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

254

void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

256

union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

258

void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

261

uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

263

void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

265

uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

267

void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

269

void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

270

void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

271

void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

272

uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

274

void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

276

uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

277

void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

279

void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

280

void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

281

void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

283

void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

284

void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

285

void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

286

uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

287

void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.h

288

uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

155

void dmub_dcn42_reset_release(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

169

void dmub_dcn42_backdoor_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

19

void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

200

void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

224

void dmub_dcn42_setup_windows(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

288

uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

293

uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

298

void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

305

uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

314

void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

323

bool dmub_dcn42_is_supported(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

330

union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

338

void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

346

bool dmub_dcn42_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

353

void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

358

uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

363

bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

378

void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

383

bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

39

void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

394

union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

402

void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

410

void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

423

void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

428

void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

497

uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

505

void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

530

void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

535

void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

540

void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

545

void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

551

void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

557

void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

562

uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

570

void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

577

void dmub_dcn42_set_gpint(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

583

bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

594

uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

599

uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

614

uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

619

void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

624

uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

629

void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

66

static void dmub_dcn42_get_fb_base_offset(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

710

bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

748

void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

753

uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.c

95

void dmub_dcn42_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

231

void dmub_srv_dcn42_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

232

void dmub_dcn42_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

233

void dmub_dcn42_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

234

void dmub_dcn42_configure_dmub_in_system_memory(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

237

void dmub_dcn42_reset(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

238

void dmub_dcn42_reset_release(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

241

void dmub_dcn42_backdoor_load(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

242

void dmub_dcn42_backdoor_load_zfb_mode(struct dmub_srv *dmub, const struct dmub_window *cw0, const struct dmub_window *cw1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

243

void dmub_dcn42_setup_windows(struct dmub_srv *dmub, const struct dmub_window *cw2, const struct dmub_window *cw3, const struct dmub_window *cw4, const struct dmub_window *cw5, const struct dmub_window *cw6, const struct dmub_window *region6);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

246

void dmub_dcn42_setup_mailbox(struct dmub_srv *dmub, const struct dmub_region *inbox1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

247

uint32_t dmub_dcn42_get_inbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

248

uint32_t dmub_dcn42_get_inbox1_rptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

249

void dmub_dcn42_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

252

void dmub_dcn42_setup_out_mailbox(struct dmub_srv *dmub, const struct dmub_region *outbox1);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

253

uint32_t dmub_dcn42_get_outbox1_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

254

void dmub_dcn42_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

257

void dmub_dcn42_setup_outbox0(struct dmub_srv *dmub, const struct dmub_region *outbox0);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

258

uint32_t dmub_dcn42_get_outbox0_wptr(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

259

void dmub_dcn42_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

262

void dmub_dcn42_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

263

void dmub_dcn42_clear_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

264

uint32_t dmub_dcn42_read_inbox0_ack_register(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

267

void dmub_dcn42_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

268

uint32_t dmub_dcn42_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

269

void dmub_dcn42_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, union dmub_rb_cmd *cmd);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

270

void dmub_dcn42_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

271

void dmub_dcn42_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

272

void dmub_dcn42_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

274

void dmub_dcn42_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

275

void dmub_dcn42_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

276

void dmub_dcn42_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

277

uint32_t dmub_dcn42_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

278

void dmub_dcn42_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

279

uint32_t dmub_dcn42_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

282

void dmub_dcn42_set_gpint(struct dmub_srv *dmub, union dmub_gpint_data_register reg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

283

bool dmub_dcn42_is_gpint_acked(struct dmub_srv *dmub, union dmub_gpint_data_register reg);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

284

uint32_t dmub_dcn42_get_gpint_response(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

285

uint32_t dmub_dcn42_get_gpint_dataout(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

288

bool dmub_dcn42_is_hw_init(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

289

bool dmub_dcn42_is_supported(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

290

bool dmub_dcn42_is_hw_powered_up(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

291

bool dmub_dcn42_should_detect(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

295

union dmub_fw_boot_status dmub_dcn42_get_fw_boot_status(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

296

union dmub_fw_boot_options dmub_dcn42_get_fw_boot_option(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

299

uint32_t dmub_dcn42_get_current_time(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

300

void dmub_dcn42_get_diagnostic_data(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

301

bool dmub_dcn42_get_preos_fw_info(struct dmub_srv *dmub);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42.h

32

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c

16

void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h

11

void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.h

9

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

106

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

74

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c

91

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

114

void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

117

void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

120

void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift,

drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h

31

struct dmub_srv;

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1014

enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1038

static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1057

enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1095

enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1122

dmub_srv_send_gpint_command(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1154

enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1170

enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1186

enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1200

enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1214

enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1249

bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1256

bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1264

bool dmub_srv_should_detect(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1272

enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1281

enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1298

enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1308

void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1317

void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1325

enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1360

void dmub_srv_cmd_get_response(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1373

static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1384

static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1405

enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1420

enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1447

enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

1477

bool dmub_srv_get_preos_info(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

205

static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

550

enum dmub_status dmub_srv_create(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

601

void dmub_srv_destroy(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

627

dmub_srv_calc_region_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

684

enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

718

enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

732

enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

748

enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

910

enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

937

enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

959

enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

985

bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub)

drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

996

enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/dmub/src/dmub_srv_stat.c

46

enum dmub_status dmub_srv_stat_get_notification(struct dmub_srv *dmub,

drivers/gpu/drm/amd/display/modules/power/power_abm.c

701

} else if (dc->ctx->dmub_srv) {