drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

289

/ dml_pow(

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3468

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c

3491

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

313

/ dml_pow(

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3576

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c

3599

dml_pow((locals->ReturnBWToDCNPerState * locals->UrgentLatency

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1305

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1306

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1337

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1338

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1380

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1381

disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1382

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1383

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1384

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1385

disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1387

disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1388

disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1393

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1400

< (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1406

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1424

/ (double) vratio_l * dml_pow(2, 2)));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1425

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1429

/ (double) vratio_c * dml_pow(2, 2)));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1430

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1434

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1439

/ (double) vratio_l * dml_pow(2, 2)));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1440

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1447

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1448

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1452

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1453

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1460

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1461

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1468

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1469

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1476

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1477

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1483

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1484

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1494

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1496

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1498

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1500

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1502

(unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1504

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1506

(unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1508

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1510

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1524

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1638

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

1668

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

922

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

924

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

928

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

937

disp_dlg_regs->min_dst_y_next_start = (unsigned int) ((double) dlg_vblank_start * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c

938

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1306

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1307

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1338

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1339

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1381

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1382

disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1383

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1384

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1385

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1386

disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1388

disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1389

disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1394

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1401

< (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1407

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1425

/ (double) vratio_l * dml_pow(2, 2)));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1426

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1430

/ (double) vratio_c * dml_pow(2, 2)));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1431

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1435

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1440

/ (double) vratio_l * dml_pow(2, 2)));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1441

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1448

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1449

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1453

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1454

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1461

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1462

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1469

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1470

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1477

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1478

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1484

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1485

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1495

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1497

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1499

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1501

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1503

(unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1505

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1507

(unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1509

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1511

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1525

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1639

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

1669

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

922

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

924

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

928

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

938

+ min_dst_y_ttu_vblank) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c

939

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1369

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1370

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1405

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1406

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1450

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1451

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1452

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1453

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1454

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1455

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1457

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1458

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1469

disp_dlg_regs->refcyc_per_pte_group_vblank_l >= (unsigned int)dml_pow(2, 13))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1472

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1479

disp_dlg_regs->refcyc_per_pte_group_vblank_c >= (unsigned int)dml_pow(2, 13))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1483

< (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1492

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1511

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1512

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1515

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1516

disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1518

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1519

disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1521

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1522

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1524

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1525

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1527

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1528

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1532

/ (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1533

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1538

(unsigned int)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1543

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1544

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1555

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1556

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1560

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1561

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1568

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1569

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1576

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1577

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)dml_pow(2, 23) - 1;

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1584

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1585

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1591

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1592

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1602

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1604

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1606

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1608

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1610

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1612

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1614

(unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1616

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1618

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1621

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1632

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1752

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

1788

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

968

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

970

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

974

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

983

disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c

984

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1043

(unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1045

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1056

) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1057

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1221

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1480

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1481

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1512

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1513

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1556

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1557

disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1558

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1559

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1560

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1561

disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1563

disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1564

disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1574

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1581

< (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1587

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1606

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1607

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1610

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1611

disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1613

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1614

disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1616

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1617

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1619

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1620

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1623

/ (double)vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1624

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1628

/ (double)vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1629

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int)dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1633

(unsigned int)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1638

/ (double)vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1639

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1648

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1649

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1653

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1654

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1661

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1662

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1669

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1670

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1677

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1678

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1684

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1685

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1695

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1697

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1699

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1701

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1703

(unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1705

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1707

(unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1709

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1711

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1714

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

1725

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

851

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c

881

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1097

} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1326

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1363

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1411

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1412

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1413

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1414

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1415

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1416

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1418

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1419

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1427

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1431

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1435

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1449

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1450

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1453

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1454

disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1456

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1457

disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1459

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1460

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1462

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1463

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1465

disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1466

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1468

disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1469

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1474

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1478

disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1479

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1481

disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1482

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1486

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1487

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1490

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1491

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1496

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1497

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1502

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1503

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1508

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1512

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1521

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1522

disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1523

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1524

disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1525

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1526

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1527

disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1528

disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1531

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1534

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

1545

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

828

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

843

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

983

disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

984

disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

991

disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c

993

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1068

disp_dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1069

disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1078

disp_dlg_regs->min_dst_y_next_start = (unsigned int)(vba__min_dst_y_next_start * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1080

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1185

} ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1414

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1451

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1499

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1500

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1501

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1502

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1503

disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1504

disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1506

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1507

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1515

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1519

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1523

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1537

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(get_refcyc_per_vm_req_vblank_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1538

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(get_refcyc_per_vm_req_flip_in_us(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1541

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1542

disp_dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1544

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1545

disp_dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1547

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1548

disp_dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1550

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1551

disp_dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1553

disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1554

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1556

disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1557

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1562

(unsigned int) dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1566

disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l / (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1567

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1569

disp_dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int) ((double) meta_row_height_c / (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1570

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1574

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1575

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1578

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1579

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1584

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1585

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1590

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1591

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1596

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1600

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13)); ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1609

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1610

disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1611

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1612

disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1613

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1614

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1615

disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1616

disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1619

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1622

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

1633

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

914

ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c

928

ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

274

dlg_regs->ref_freq_to_pix_freq = (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

275

dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal * dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

344

ASSERT(dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

440

dlg_regs->min_dst_y_next_start = (unsigned int)(min_dst_y_next_start * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

441

ASSERT(dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

445

dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

446

dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

447

dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

448

dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

449

dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

451

dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

452

dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

464

pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

466

pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10)); // From VBA

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

503

dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)(dst_y_per_pte_row_nom_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

504

dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)(dst_y_per_pte_row_nom_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

505

dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)(dst_y_per_meta_row_nom_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

506

dlg_regs->dst_y_per_meta_row_nom_c = (unsigned int)(dst_y_per_meta_row_nom_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

531

ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

532

ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

533

ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

534

ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

536

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

537

ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

554

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

555

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

556

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

557

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

558

if (dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

559

dlg_regs->refcyc_per_vm_group_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

561

if (dlg_regs->refcyc_per_vm_group_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

562

dlg_regs->refcyc_per_vm_group_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

564

if (dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

565

dlg_regs->refcyc_per_vm_req_vblank = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

567

if (dlg_regs->refcyc_per_vm_req_flip >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

568

dlg_regs->refcyc_per_vm_req_flip = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

571

ASSERT(dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

572

ASSERT(dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

574

if (dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

577

__func__, dlg_regs->dst_y_per_pte_row_nom_c, (unsigned int)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

580

ASSERT(dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

581

ASSERT(dlg_regs->dst_y_per_meta_row_nom_c < (unsigned int)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

583

if (dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

584

dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

586

if (dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

587

dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

589

ASSERT(dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

591

ASSERT(dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

594

if (dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

595

dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

597

if (dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

598

dlg_regs->refcyc_per_meta_chunk_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

600

ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

601

ASSERT(dlg_regs->refcyc_per_meta_chunk_vblank_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

602

ASSERT(dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

603

ASSERT(dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

604

ASSERT(dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

605

ASSERT(dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

606

ASSERT(ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

607

ASSERT(ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_rq_dlg_calc_32.c

608

ASSERT(ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1156

(unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1158

* dml_pow(2, 8));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1161

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1178

+ min_dst_y_ttu_vblank) * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1179

ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1443

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1453

disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1464

disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1468

disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1522

disp_dlg_regs->vratio_prefetch = (unsigned int) dml_pow(2, 21) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1524

disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1528

disp_dlg_regs->vratio_prefetch_c = (unsigned int) dml_pow(2, 21) - 1;

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1530

disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1535

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1540

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1545

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1562

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1563

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1566

/ (double) vratio_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1567

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_c < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1570

/ (double) vratio_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1571

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1578

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1579

disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1584

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1585

disp_dlg_regs->refcyc_per_pte_group_nom_c = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1590

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1591

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1692

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1693

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1731

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1732

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1774

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1776

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1778

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1779

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1811

(unsigned int) (refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1813

* dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1815

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1816

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1863

(unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1864

ASSERT(refcyc_per_req_delivery_pre_cur0 < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1898

(unsigned int) (refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1899

ASSERT(refcyc_per_req_delivery_cur0 < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1907

ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1910

ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c

1921

ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

2631

*dpte_row_height = (dml_uint_t)(dml_min(128, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1))));

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

2635

dml_print("DML::%s: dpte_row_height term 4 = %u\n", __func__, (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * *PixelPTEReqWidth / Pitch), 1)));

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c

2642

*dpte_row_height_linear = (dml_uint_t)dml_pow(2.0, (int)dml_floor(dml_log2(PTEBufferSizeInRequests * PixelPTEReqWidth_linear / Pitch), 1));

drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.h

49

__DML_DLL_EXPORT__ dml_float_t dml_pow(dml_float_t base, int exp);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

315

ASSERT(disp_dlg_regs->refcyc_h_blank_end < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

317

disp_dlg_regs->ref_freq_to_pix_freq = (dml_uint_t)(ref_freq_to_pix_freq * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

318

temp = dml_pow(2, 8);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

411

disp_dlg_regs->min_dst_y_next_start = (dml_uint_t)((dml_float_t) min_dst_y_next_start * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

412

ASSERT(disp_dlg_regs->min_dst_y_next_start < (dml_uint_t)dml_pow(2, 18));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

416

disp_dlg_regs->dst_y_prefetch = (dml_uint_t)(dst_y_prefetch * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

417

disp_dlg_regs->dst_y_per_vm_vblank = (dml_uint_t)(dst_y_per_vm_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

418

disp_dlg_regs->dst_y_per_row_vblank = (dml_uint_t)(dst_y_per_row_vblank * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

419

disp_dlg_regs->dst_y_per_vm_flip = (dml_uint_t)(dst_y_per_vm_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

420

disp_dlg_regs->dst_y_per_row_flip = (dml_uint_t)(dst_y_per_row_flip * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

422

disp_dlg_regs->vratio_prefetch = (dml_uint_t)(vratio_pre_l * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

423

disp_dlg_regs->vratio_prefetch_c = (dml_uint_t)(vratio_pre_c * dml_pow(2, 19));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

432

disp_dlg_regs->refcyc_per_vm_req_vblank = (dml_uint_t)(dml_get_refcyc_per_vm_req_vblank_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

433

disp_dlg_regs->refcyc_per_vm_req_flip = (dml_uint_t)(dml_get_refcyc_per_vm_req_flip_in_us(mode_lib, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

454

disp_dlg_regs->dst_y_per_pte_row_nom_l = (dml_uint_t)(dst_y_per_pte_row_nom_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

455

disp_dlg_regs->dst_y_per_pte_row_nom_c = (dml_uint_t)(dst_y_per_pte_row_nom_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

456

disp_dlg_regs->dst_y_per_meta_row_nom_l = (dml_uint_t)(dst_y_per_meta_row_nom_l * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

457

disp_dlg_regs->dst_y_per_meta_row_nom_c = (dml_uint_t)(dst_y_per_meta_row_nom_c * dml_pow(2, 2));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

482

disp_ttu_regs->refcyc_per_req_delivery_pre_l = (dml_uint_t)(refcyc_per_req_delivery_pre_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

483

disp_ttu_regs->refcyc_per_req_delivery_l = (dml_uint_t)(refcyc_per_req_delivery_l * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

484

disp_ttu_regs->refcyc_per_req_delivery_pre_c = (dml_uint_t)(refcyc_per_req_delivery_pre_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

485

disp_ttu_regs->refcyc_per_req_delivery_c = (dml_uint_t)(refcyc_per_req_delivery_c * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

486

disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = (dml_uint_t)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

487

disp_ttu_regs->refcyc_per_req_delivery_cur0 = (dml_uint_t)(refcyc_per_req_delivery_cur0 * dml_pow(2, 10));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

504

ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

505

ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

506

ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

507

ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

508

if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

509

disp_dlg_regs->refcyc_per_vm_group_vblank = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

511

if (disp_dlg_regs->refcyc_per_vm_group_flip >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

512

disp_dlg_regs->refcyc_per_vm_group_flip = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

514

if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

515

disp_dlg_regs->refcyc_per_vm_req_vblank = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

517

if (disp_dlg_regs->refcyc_per_vm_req_flip >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

518

disp_dlg_regs->refcyc_per_vm_req_flip = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

522

ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

523

ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (dml_uint_t)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

525

if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (dml_uint_t)dml_pow(2, 17)) { // FIXME what so special about chroma, can we just assert?

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

526

dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u > register max U15.2 %u\n", __func__, disp_dlg_regs->dst_y_per_pte_row_nom_c, (dml_uint_t)dml_pow(2, 17) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

529

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (dml_uint_t)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

530

ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_c < (dml_uint_t)dml_pow(2, 17));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

532

if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

533

disp_dlg_regs->refcyc_per_pte_group_nom_l = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

535

if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

536

disp_dlg_regs->refcyc_per_pte_group_nom_c = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

538

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

540

ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

543

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

544

disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

546

if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (dml_uint_t)dml_pow(2, 23))

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

547

disp_dlg_regs->refcyc_per_meta_chunk_nom_c = (dml_uint_t)(dml_pow(2, 23) - 1);

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

549

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

550

ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

551

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

552

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

553

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

554

ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (dml_uint_t)dml_pow(2, 13));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

555

ASSERT(disp_ttu_regs->qos_level_low_wm < (dml_uint_t) dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

556

ASSERT(disp_ttu_regs->qos_level_high_wm < (dml_uint_t) dml_pow(2, 14));

drivers/gpu/drm/amd/display/dc/dml2_0/dml_display_rq_dlg_calc.c

557

ASSERT(disp_ttu_regs->min_ttu_vblank < (dml_uint_t) dml_pow(2, 24));