drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

467

struct dmcu_firmware_header_v1_0 dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1314

struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1413

if (dmcu)

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1414

hw_params.psp_version = dmcu->psp_version;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1455

if (dmcu && abm) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1456

dmcu->funcs->dmcu_init(dmcu);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

1457

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3000

struct dmcu *dmcu = NULL;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3002

dmcu = adev->dm.dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3027

if (dmcu) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

3028

if (!dmcu_load_iram(dmcu, params))

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

206

struct dmcu *dmcu = clk_mgr_dce->base.ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

234

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

235

dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

109

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

126

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

128

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

63

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

94

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c

96

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

129

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

137

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c

139

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

229

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

339

dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c

341

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

143

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

246

dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

248

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

147

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

155

if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c

157

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

206

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

323

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c

325

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

645

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

854

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c

856

dmcu->funcs->set_psr_wait_loop(dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1093

struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1231

if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

1233

block_sequence[num_steps].params.update_psr_wait_loop_params.dmcu = dmcu;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

756

params->update_psr_wait_loop_params.dmcu->funcs->set_psr_wait_loop(

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c

757

params->update_psr_wait_loop_params.dmcu,

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.h

71

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

1541

if (dc->res_pool->dmcu != NULL)

drivers/gpu/drm/amd/display/dc/core/dc.c

1542

dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;

drivers/gpu/drm/amd/display/dc/core/dc.c

516

dc_stream_forward_dmcu_crc_window(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/core/dc.c

520

dmcu->funcs->stop_crc_win_update(dmcu, mux_mapping);

drivers/gpu/drm/amd/display/dc/core/dc.c

522

dmcu->funcs->forward_crc_window(dmcu, rect, mux_mapping);

drivers/gpu/drm/amd/display/dc/core/dc.c

529

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

549

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

556

else if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/core/dc.c

557

dc_stream_forward_dmcu_crc_window(dmcu, rect, &mux_mapping, is_stop);

drivers/gpu/drm/amd/display/dc/core/dc.c

6277

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/core/dc.c

6279

if (dmcu)

drivers/gpu/drm/amd/display/dc/core/dc.c

6280

return dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/dc.h

854

bool dmcu: 1;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

35

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

37

if (dmcu &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

38

dmcu->funcs->is_dmcu_initialized(dmcu) &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

39

dmcu->funcs->send_edid_cea) {

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

40

return dmcu->funcs->send_edid_cea(dmcu,

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

52

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

54

if (dmcu &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

55

dmcu->funcs->is_dmcu_initialized(dmcu) &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

56

dmcu->funcs->recv_edid_cea_ack) {

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

57

return dmcu->funcs->recv_edid_cea_ack(dmcu, offset);

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

68

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

70

if (dmcu &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

71

dmcu->funcs->is_dmcu_initialized(dmcu) &&

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

72

dmcu->funcs->recv_amd_vsdb) {

drivers/gpu/drm/amd/display/dc/dc_edid_parser.c

73

return dmcu->funcs->recv_amd_vsdb(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1002

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

107

static void dce_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1076

struct dmcu *base = &dmcu_dce->base;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

109

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1103

struct dmcu *dce_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1124

struct dmcu *dcn10_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1145

struct dmcu *dcn20_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1166

struct dmcu *dcn21_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1187

void dce_dmcu_destroy(struct dmcu **dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1189

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

1192

*dmcu = NULL;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

130

static void dce_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

132

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

156

dce_get_dmcu_psr_state(dmcu, &state);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

169

static bool dce_dmcu_setup_psr(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

173

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

251

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

263

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

268

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

281

static bool dce_is_dmcu_initialized(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

283

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

297

struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

300

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

303

if (dmcu->cached_wait_loop_number == wait_loop_number)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

307

if (!dce_is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

315

dmcu->cached_wait_loop_number = wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

316

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

326

struct dmcu *dmcu, unsigned int *psr_wait_loop_number)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

328

*psr_wait_loop_number = dmcu->cached_wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

332

static void dcn10_get_dmcu_version(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

334

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

34

#define TO_DCE_DMCU(dmcu)\

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

346

dmcu->dmcu_version.interface_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

347

dmcu->dmcu_version.abm_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

348

dmcu->dmcu_version.psr_version = REG_READ(DMCU_IRAM_RD_DATA);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

349

dmcu->dmcu_version.build_version = ((REG_READ(DMCU_IRAM_RD_DATA) << 8) |

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

35

container_of(dmcu, struct dce_dmcu, base)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

358

static void dcn10_dmcu_enable_fractional_pwm(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

361

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

380

static bool dcn10_dmcu_init(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

382

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

383

const struct dc_config *config = &dmcu->ctx->dc->config;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

385

struct dc_context *ctx = dmcu->ctx;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

397

dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

408

switch (dmcu->dmcu_state) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

435

dmcu->dmcu_state = REG_READ(DC_DMCU_SCRATCH);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

438

if (dmcu->dmcu_state == DMCU_RUNNING) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

440

dcn10_get_dmcu_version(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

443

dcn10_dmcu_enable_fractional_pwm(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

463

static bool dcn21_dmcu_init(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

465

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

468

if (dmcu->auto_load_dmcu && dmcub_psp_version == 0) {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

472

return dcn10_dmcu_init(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

475

static bool dcn10_dmcu_load_iram(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

480

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

484

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

520

static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, enum dc_psr_state *state)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

522

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

527

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

547

static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable, bool wait)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

549

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

557

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

582

dcn10_get_dmcu_psr_state(dmcu, &state);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

600

static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

604

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

614

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

690

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

702

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

707

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

72

static bool dce_dmcu_init(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

725

struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

728

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

732

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

74

(void)dmcu;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

741

dmcu->cached_wait_loop_number = wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

742

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

753

struct dmcu *dmcu, unsigned int *psr_wait_loop_number)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

755

*psr_wait_loop_number = dmcu->cached_wait_loop_number;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

759

static bool dcn10_is_dmcu_initialized(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

762

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

769

static bool dcn20_lock_phy(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

771

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

774

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

79

static bool dce_dmcu_load_iram(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

792

static bool dcn20_unlock_phy(struct dmcu *dmcu)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

794

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

797

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

815

static bool dcn10_send_edid_cea(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

821

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

825

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

84

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

856

static bool dcn10_get_scp_results(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

862

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

865

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

879

static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

887

if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3]))

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

907

static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

912

if (!dcn10_get_scp_results(dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

931

static void dcn10_forward_crc_window(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

935

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

942

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

964

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

967

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

970

dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

981

static void dcn10_stop_crc_win_update(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

984

struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

990

if (dmcu->dmcu_state != DMCU_RUNNING)

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

234

struct dmcu base;

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

305

struct dmcu *dce_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

311

struct dmcu *dcn10_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

317

struct dmcu *dcn20_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

323

struct dmcu *dcn21_dmcu_create(

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

329

void dce_dmcu_destroy(struct dmcu **dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3003

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3066

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3067

if (dmcu != NULL && abm != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3068

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3392

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3402

if (dmcu)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3403

fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3488

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3537

if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3538

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3546

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3547

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3558

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3564

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3565

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3574

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

3575

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1809

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1921

if (dmcu != NULL && !dmcu->auto_load_dmcu)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1922

dmcu->funcs->dmcu_init(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1925

if (abm != NULL && dmcu != NULL)

drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c

1926

abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

183

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

191

if (dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

216

struct dmcu *dmcu = pipe_ctx->stream->ctx->dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

224

if (dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c

259

if (dc->dc->res_pool->dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

667

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c

77

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

512

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

518

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

519

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

528

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c

529

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1426

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1432

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1433

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1442

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c

1443

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1811

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1817

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1818

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1832

if (dmcu != NULL && dmcu->funcs->unlock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

1833

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

83

if (dc->debug.enable_mem_low_power.bits.dmcu) {

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1098

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1104

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1105

dmcu->funcs->lock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1119

else if (dmcu != NULL && dmcu->funcs->lock_phy)

drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c

1120

dmcu->funcs->unlock_phy(dmcu);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

329

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

60

bool (*dmcu_init)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

61

bool (*load_iram)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

65

void (*set_psr_enable)(struct dmcu *dmcu, bool enable, bool wait);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

66

bool (*setup_psr)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

69

void (*get_psr_state)(struct dmcu *dmcu, enum dc_psr_state *dc_psr_state);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

70

void (*set_psr_wait_loop)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

72

void (*get_psr_wait_loop)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

74

bool (*is_dmcu_initialized)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

75

bool (*lock_phy)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

76

bool (*unlock_phy)(struct dmcu *dmcu);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

77

bool (*send_edid_cea)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

82

bool (*recv_amd_vsdb)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

86

bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset);

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

88

void (*forward_crc_window)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h

91

void (*stop_crc_win_update)(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1211

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1214

if (dmcu)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1215

fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

584

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

620

else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

622

dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

632

struct dmcu *dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

641

else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

642

dmcu->funcs->get_psr_state(dmcu, state);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

689

struct dmcu *dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

729

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

732

if (!dmcu && !psr)

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

895

link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1093

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

1097

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

841

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

842

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1425

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

1429

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

878

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

879

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1313

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

1317

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

843

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c

844

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1141

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

1145

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

664

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce120/dce120_resource.c

665

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1181

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1185

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1378

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

1382

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

877

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

878

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

983

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

987

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1195

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1199

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1393

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

1397

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

884

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

885

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

995

pool->base.dmcu = dce_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

999

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1008

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1009

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1492

pool->base.dmcu = dcn10_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c

1496

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1216

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

1217

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2590

pool->base.dmcu = dcn20_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c

2594

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1562

pool->base.dmcu = dcn21_dmcu_create(ctx,

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

1566

if (pool->base.dmcu == NULL) {

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

782

if (pool->base.dmcu != NULL)

drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c

783

dce_dmcu_destroy(&pool->base.dmcu);

drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c

939

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c

959

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c

939

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c

934

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c

767

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c

757

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c

791

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c

771

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c

778

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c

755

.dmcu = false, // This is previously known to cause hang on S3 cycles if enabled

drivers/gpu/drm/amd/display/modules/power/power.c

196

if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2003

bool dmcu_load_iram(struct dmcu *dmcu,

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2009

if (dmcu == NULL)

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2012

if (dmcu && !dmcu->funcs->is_dmcu_initialized(dmcu))

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2017

if (dmcu->dmcu_version.abm_version == 0x24) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2019

result = dmcu->funcs->load_iram(dmcu, 0, (char *)(&ram_table),

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2021

} else if (dmcu->dmcu_version.abm_version == 0x23) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2024

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2025

dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2026

} else if (dmcu->dmcu_version.abm_version == 0x22) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2029

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2030

dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2_2);

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2034

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2035

dmcu, 0, (char *)(&ram_table), IRAM_RESERVE_AREA_START_V2);

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2038

result = dmcu->funcs->load_iram(

drivers/gpu/drm/amd/display/modules/power/power_abm.c

2039

dmcu, IRAM_RESERVE_AREA_END_V2 + 1,

drivers/gpu/drm/amd/display/modules/power/power_abm.c

674

struct dmcu *dmcu = NULL;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

693

dmcu = dc->res_pool->dmcu;

drivers/gpu/drm/amd/display/modules/power/power_abm.c

698

if (dmcu) {

drivers/gpu/drm/amd/display/modules/power/power_abm.c

700

return dmcu_load_iram(dmcu, params);

drivers/gpu/drm/amd/display/modules/power/power_helpers.h

143

bool dmcu_load_iram(struct dmcu *dmcu,