dmc620_pmu
#define to_dmc620_pmu(p) (container_of(p, struct dmc620_pmu, pmu))
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(dev_get_drvdata(dev));
cpumask_of(dmc620_pmu->irq->cpu));
u32 dmc620_pmu_creg_read(struct dmc620_pmu *dmc620_pmu,
return readl(dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg);
void dmc620_pmu_creg_write(struct dmc620_pmu *dmc620_pmu,
writel(val, dmc620_pmu->base + DMC620_PMU_COUNTERn_OFFSET(idx) + reg);
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
if (!test_and_set_bit(idx, dmc620_pmu->used_mask))
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
return dmc620_pmu_creg_read(dmc620_pmu,
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
dmc620_pmu_creg_write(dmc620_pmu,
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
dmc620_pmu_creg_write(dmc620_pmu,
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
dmc620_pmu_creg_write(dmc620_pmu,
struct dmc620_pmu *dmc620_pmu;
list_for_each_entry_rcu(dmc620_pmu, &irq->pmus_node, pmus_node) {
event = dmc620_pmu->events[idx];
status = readl(dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2);
status |= (readl(dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK) <<
event = dmc620_pmu->events[idx];
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2);
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK);
event = dmc620_pmu->events[idx];
static int dmc620_pmu_get_irq(struct dmc620_pmu *dmc620_pmu, int irq_num)
dmc620_pmu->irq = irq;
list_add_rcu(&dmc620_pmu->pmus_node, &irq->pmus_node);
static void dmc620_pmu_put_irq(struct dmc620_pmu *dmc620_pmu)
struct dmc620_pmu_irq *irq = dmc620_pmu->irq;
list_del_rcu(&dmc620_pmu->pmus_node);
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
dev_dbg(dmc620_pmu->pmu.dev,
event->cpu = dmc620_pmu->irq->cpu;
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
dmc620_pmu->events[idx] = event;
dmc620_pmu_creg_write(dmc620_pmu,
dmc620_pmu_creg_write(dmc620_pmu,
dmc620_pmu_creg_write(dmc620_pmu,
dmc620_pmu_creg_write(dmc620_pmu,
struct dmc620_pmu *dmc620_pmu = to_dmc620_pmu(event->pmu);
dmc620_pmu->events[idx] = NULL;
clear_bit(idx, dmc620_pmu->used_mask);
struct dmc620_pmu *dmc620_pmu;
list_for_each_entry(dmc620_pmu, &irq->pmus_node, pmus_node)
perf_pmu_migrate_context(&dmc620_pmu->pmu, irq->cpu, target);
struct dmc620_pmu *dmc620_pmu;
dmc620_pmu = devm_kzalloc(&pdev->dev,
sizeof(struct dmc620_pmu), GFP_KERNEL);
if (!dmc620_pmu)
platform_set_drvdata(pdev, dmc620_pmu);
dmc620_pmu->pmu = (struct pmu) {
dmc620_pmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
if (IS_ERR(dmc620_pmu->base))
return PTR_ERR(dmc620_pmu->base);
dmc620_pmu_creg_write(dmc620_pmu, i, DMC620_PMU_COUNTERn_CONTROL, 0);
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLKDIV2);
writel(0, dmc620_pmu->base + DMC620_PMU_OVERFLOW_STATUS_CLK);
ret = dmc620_pmu_get_irq(dmc620_pmu, irq_num);
ret = perf_pmu_register(&dmc620_pmu->pmu, name, -1);
dmc620_pmu_put_irq(dmc620_pmu);
struct dmc620_pmu *dmc620_pmu = platform_get_drvdata(pdev);
dmc620_pmu_put_irq(dmc620_pmu);
perf_pmu_unregister(&dmc620_pmu->pmu);