drm_dp_channel_eq_ok
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
if (drm_dp_channel_eq_ok(link_status, mhdp->link.num_lanes)) {
drm_dp_channel_eq_ok(status, mhdp->link.num_lanes) &&
if (drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
if (ret < 0 || !drm_dp_channel_eq_ok(link_status, it6505->lane_count) ||
if (!drm_dp_channel_eq_ok(link_status, it6505->lane_count)) {
if (!drm_dp_channel_eq_ok(status, link->lanes)) {
return !drm_dp_channel_eq_ok(link_status, dp->link.lanes);
if (drm_dp_channel_eq_ok(status, link->lanes)) {
EXPORT_SYMBOL(drm_dp_channel_eq_ok);
if (drm_dp_channel_eq_ok(lane_status, dp->link.cap.lanes)) {
ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
if (drm_dp_channel_eq_ok(link_status,
if (drm_dp_channel_eq_ok(link_status, target_lane_count)) {
if (drm_dp_channel_eq_ok(link_status,
return drm_dp_channel_eq_ok(link_status, num_lanes);
bool channel_eq_done = drm_dp_channel_eq_ok(link->link_status,
if (!drm_dp_channel_eq_ok(stat, outp->dp.lt.nr)) {
if (drm_dp_channel_eq_ok(link_status, outp->dp.lt.nr))
if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
return drm_dp_channel_eq_ok(link_status, min(port->lanes, sink_lanes));
if (!drm_dp_channel_eq_ok(status, link->lanes))
if (!drm_dp_channel_eq_ok(status, link->lanes)) {
!drm_dp_channel_eq_ok(&status[2], dp->mode.lane_cnt)) {
ce_done = drm_dp_channel_eq_ok(link_status, lane_cnt);
bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],