dma_wd
if (!MACH_IS_MEDUSA && hwreg_present(&dma_wd.fdc_speed) &&
hwreg_write(&dma_wd.fdc_speed, 0)) {
#define st_dma dma_wd
dma_wd.dma_lo = (unsigned char)paddr;
dma_wd.dma_md = (unsigned char)paddr;
dma_wd.dma_hi = (unsigned char)paddr;
dma_wd.dma_mode_status = 0x90 | rwflag;
dma_wd.dma_mode_status = 0x90 | (rwflag ^ 0x100);
dma_wd.dma_mode_status = 0x90 | rwflag;
dma_wd.fdc_acces_seccount = read_track ? SUDT->spt : 1;
dma_wd.dma_mode_status = FDCSELREG_STP | rwflag;
dma_wd.fdc_acces_seccount =
addr = dma_wd.dma_lo & 0xff;
addr |= (dma_wd.dma_md & 0xff) << 8;
addr |= (dma_wd.dma_hi & 0xff) << 16;
dma_wd.dma_mode_status = 0x90;
if (!(dma_wd.dma_mode_status & 0x01)) {
dma_wd.fdc_speed = SUDT->fdc_speed;
dma_wd.dma_lo = (unsigned char)paddr;
dma_wd.dma_md = (unsigned char)paddr;
dma_wd.dma_hi = (unsigned char)paddr;
dma_wd.dma_mode_status = 0x190;
dma_wd.dma_mode_status = 0x90;
dma_wd.dma_mode_status = 0x190;
dma_wd.fdc_acces_seccount = BUFFER_SIZE/512;
dma_wd.dma_mode_status = FDCSELREG_STP | 0x100;
dma_wd.fdc_acces_seccount = FDCCMD_WRTRA | get_head_settle_flag();
dma_wd.fdc_speed = 0;
dma_wd.dma_mode_status = 0x80 | (reg); \
__val = dma_wd.fdc_acces_seccount; \
dma_wd.dma_mode_status = 0x80 | (reg); \
dma_wd.fdc_acces_seccount = (val); \
dma_wd.fdc_speed = UDT->fdc_speed;
dma_wd.fdc_speed = 0; /* always seek with 8 Mhz */
dma_wd.fdc_speed = SUDT->fdc_speed;
dma_wd.fdc_speed = 0; /* always seek witch 8 Mhz */
dma_wd.fdc_speed = SUDT->fdc_speed;
dma_wd.dma_mode_status = (u_short)reg;
result = (u8)dma_wd.fdc_acces_seccount;
dma_wd.dma_mode_status = (u_short)reg;
dma_wd.fdc_acces_seccount = (u_short)value;