dma_ctrl
if (hwreg_present(&tt_scc_dma.dma_ctrl) &&
(tt_scc_dma.dma_ctrl = 0x01, (tt_scc_dma.dma_ctrl & 1) == 1) &&
(tt_scc_dma.dma_ctrl = 0x00, (tt_scc_dma.dma_ctrl & 1) == 0)
u_short dma_ctrl;
volatile unsigned long dma_ctrl;
volatile u32 dma_ctrl; /* Main DMA control reg */
u32 ctl = sgimc->dma_ctrl;
if (!(sgimc->dma_ctrl & 0x100)) /* Xlate-bit clear ? */
REGSTORE(regs->dma_ctrl, 0);
unsigned int dma_ctrl; /* 0x10 DMA */
u32 dma_ctrl;
ret = xe_mmio_wait32(mmio, DMA_CTRL, START_DMA, 0, 100000, &dma_ctrl,
xe_uc_fw_type_repr(uc_fw->type), dma_ctrl);
u32 dma_ctrl;
fb_desc->dma_ctrl = ctrl;
u32 dma_ctrl;
dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
u32 addr1, cmd, dma_ctrl;
dma_ctrl = DMA_MST_CTRL_GO | DMA_MST_CTRL_PERF_EN |
dma_ctrl |= DMA_MST_CTRL_EN_A;
dma_ctrl |= DMA_MST_CTRL_EN_B;
dma_ctrl |= DMA_MST_CTRL_IN | DMA_MST_CTRL_REUSE;
dma_ctrl |= DMA_MST_CTRL_OUT;
writel_relaxed(dma_ctrl, ctrl->regs + DMA_MST_CTRL);
union gmac_dma_ctrl dma_ctrl;
dma_ctrl.bits32 = readl(dma_ctrl_reg);
dma_ctrl.bits.rd_enable = 1;
dma_ctrl.bits.td_enable = 1;
dma_ctrl.bits.loopback = 0;
dma_ctrl.bits.drop_small_ack = 0;
dma_ctrl.bits.rd_insert_bytes = NET_IP_ALIGN;
dma_ctrl.bits.rd_prot = HPROT_DATA_CACHE | HPROT_PRIVILIGED;
dma_ctrl.bits.rd_burst_size = HBURST_INCR8;
dma_ctrl.bits.rd_bus = HSIZE_8;
dma_ctrl.bits.td_prot = HPROT_DATA_CACHE;
dma_ctrl.bits.td_burst_size = HBURST_INCR8;
dma_ctrl.bits.td_bus = HSIZE_8;
writel(dma_ctrl.bits32, dma_ctrl_reg);
union gmac_dma_ctrl dma_ctrl;
dma_ctrl.bits32 = readl(dma_ctrl_reg);
dma_ctrl.bits.rd_enable = 0;
dma_ctrl.bits.td_enable = 0;
writel(dma_ctrl.bits32, dma_ctrl_reg);
dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
dma_ctrl = 0;
dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
u32 dma_ctrl, txqctl;
u32 dma_ctrl = DMAR_REQ_PRI;
dma_ctrl |= IN_ORDER_MODE;
dma_ctrl |= ENH_ORDER_MODE;
dma_ctrl |= OUT_ORDER_MODE;
dma_ctrl |= (((u32)adpt->dmar_block) << REGRDBLEN_SHFT) &
dma_ctrl |= (((u32)adpt->dmaw_block) << REGWRBLEN_SHFT) &
dma_ctrl |= (((u32)adpt->dmar_dly_cnt) << DMAR_DLY_CNT_SHFT) &
dma_ctrl |= (((u32)adpt->dmaw_dly_cnt) << DMAW_DLY_CNT_SHFT) &
writel(dma_ctrl, adpt->base + EMAC_DMA_CTRL);
priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl &= ~METH_DMA_RX_EN;
mace->eth.dma_ctrl = priv->dma_ctrl;
if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
mace->eth.dma_ctrl = priv->dma_ctrl;
priv->dma_ctrl |= METH_DMA_TX_INT_EN;
mace->eth.dma_ctrl = priv->dma_ctrl;
unsigned long dma_ctrl;
priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
mace->eth.dma_ctrl = priv->dma_ctrl;
__le32 dma_ctrl;
P54U_WRITE(NET2280_DEV_U32, &devreg->dma_ctrl,
dma_stat = tt_scsi_dma.dma_ctrl;
tt_scsi_dma.dma_ctrl = 0;
tt_scsi_dma.dma_ctrl = 0;
tt_scsi_dma.dma_ctrl = dir;
tt_scsi_dma.dma_ctrl = dir | 2;
tt_scsi_dma.dma_ctrl = 0;
tt_scsi_dma.dma_ctrl = 0;
u16 imr, dma_ctrl;
dma_ctrl = DW_SPI_DMACR_TDMAE;
dma_ctrl |= DW_SPI_DMACR_RDMAE;
dw_writel(dws, DW_SPI_DMACR, dma_ctrl);
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
writel(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));
tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id));
writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));
u32 dma_ctrl;
u32 dma_ctrl; /* this_78 (ADB), this_7c (WT) */
dma->dma_ctrl);
dma->dma_ctrl =
((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
dma->dma_ctrl =
(dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
dma->dma_ctrl =
(dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
dma->dma_ctrl =
(dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
dma->dma_ctrl);
dma->dma_ctrl);
dma->dma_ctrl);
dma->dma_ctrl);
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
dma->dma_ctrl = 0;
dma->dma_ctrl =
((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
dma->dma_ctrl =
(dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
dma->dma_ctrl |= (1 << DIR_SHIFT);
dma->dma_ctrl =
(dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
dma->dma_ctrl);
dma->dma_ctrl);
dma->dma_ctrl);
u32 dma_ctrl;
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
u32 dma_ctrl;
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl,
!(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK),
u32 dma_ctrl;
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK;
dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
u32 dma_ctrl;
dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK;
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);
dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK;
acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0