drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1037

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1040

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1052

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_CONTROL, tg110->offsets.crtc, value);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1053

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1054

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, value);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

1112

dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_CRC_CNTL,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

261

dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_GSL_WINDOW, tg110->offsets.crtc, 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

425

dm_write_reg_soc15(tg->ctx, mmD1VGA_CONTROL, offset, value);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

519

dm_write_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

529

dm_write_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

654

dm_write_reg_soc15(tg->ctx,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

676

dm_write_reg_soc15(

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

750

dm_write_reg_soc15(tg->ctx, mmCRTC0_CRTC_BLANK_CONTROL,

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

911

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS, tg110->offsets.crtc, 0);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

950

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);

drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c

963

dm_write_reg_soc15(ctx, mmCRTC0_CRTC_TEST_PATTERN_COLOR, tg110->offsets.crtc, value);